exam 1

Does Behavioral description give any hints about how the circuit should be implemented?

Does Behavioral description give any hints about how the circuit should be implemented?

No

The statement in an always block are executed:

whenever one or more signals in the sensitivity list change

The statements in a procedural block (always in Verilog) are executed:

sequentially

We can use functional description inside a procedural block

True

We can instantiate modules inside a procedural block

False

A test bench can be synthesized

False

A testbench has no inputs and output ports

True

Exhaustive Verification applies

all possible input combinations

The initial verilog procedural block is executed

only once

the signals assigned a value inside a procedural block (always in verilog) have to be declared of type

Reg

Which simulation type is more accurate?

Timing simulation

Which is the first design step in the design flow?

Design entry/capture

Which HDL was created first for documentation purpose?

VHDL

Which type of language can describe both concurrent and sequential events?

HDLs

Which language was created from modeling/simulation purpose?

Verilog

VHDL logic operators used:

AND, OR, NOT, XOR, ETC

A VHDL entity contains the component interface information

True

VHDL does not have built-in gate-level primitives

True

A VHDL component is comprised of:

one entity and one or more architecture

High impedance or tri-stated outputs are used to transfer data

from multiple sources to one destination

if/else and case statements can be nested

True

The sensitivity list should contain all signals used inside the process on the right-hand side of assignments

True

All project files that contain descriptions belong automatically to the work library

True

Behavioral description uses

procedural statements

The statements in a VHDL process are excuted

Sequentially

In named (or explicit) association (or port mapping), the order of associations

does not matter

multibit signals in Verilog are described as

vectors

In an RCA, the carry-outs ripples from LSB to MSB

True

To create a parameterized descriptions using module instances, :

We need to use the Generate For loop/construct

In Verilog, the size of an instance using a parametrized module can be chosen:

by providing a new value for the parameters at the time of instantiation

In VHDL, a generic component can be resized from the default value(s) at instantiation time by :

providing another value for the generics

In a RCA, the cout is known after all carries have propagated from

LSB to the MSB position

In VHDL, generic mapping maps

generics to positive integer values

To create generic descriptions using component instances

we can use the VHDL For Generate loop in the concurrent block of code

Multi-bit signals in VHDL are described as

Vectors