CMOS Digital VLSI Design - Combinational Logic Design Review

These flashcards cover key concepts related to CMOS Digital VLSI design focusing on combinational logic, including Ratioed Logic, DCVSL, Pass-Transistor Logic, Dynamic Logic, and Domino Logic.

What is Ratioed Logic in terms of transistor count and power dissipation?

Ratioed Logic reduces transistor count but results in increased static power dissipation.

What is the function of Differential Cascode Voltage Switch Logic (DCVSL)?

DCVSL eliminates static power dissipation and provides rail-to-rail swing using differential logic and positive feedback.

What are the advantages of Differential Pass-Transistor Logic (DPL)?

DPL accepts true and complementary inputs and produces true and complementary outputs, resulting in a transistor count reduction.

What is a key limitation of Pass-Transistor Logic regarding high output?

NMOS in pass-transistor logic is poor in pulling a node to VDD, leading to an output of VDD-VT instead of VDD.

What are the phases of operation in Dynamic CMOS Logic?

Dynamic CMOS logic operates in two phases: pre-charge and evaluation.

What is the main issue about Charge Leakage in Dynamic Logic?

Charge Leakage occurs when the output should be at VDD during evaluation, but the charge leaks away due to leakage currents.

How do you address the Clock Feedthrough issue in Dynamic Logic?

Clock Feedthrough is addressed by managing the capacitive coupling between the clock input of precharge devices and the dynamic output node.

What is Domino Logic and its structure?

Domino Logic consists of an n-type dynamic logic block followed by a static inverter to increase noise immunity.

What challenges does Domino Logic face in terms of logic types?

Domino Logic can only implement non-inverting logic, which is a major limitation.

What is np-CMOS in the context of dynamic logic design?

np-CMOS is an alternative approach that combines n-tree and p-tree dynamic logic.