b) The Fetch-Decode-Execute Cycle

What is the fetch decode cycle?

It is the sequence of operations that are completed in order to execute an instruction.

What occurs in the fetch phase?

• Address from the PC is copied to MAR

• Instruction held at that address is copied to MDR by data bus

• Simultaneously, the contents of the PC are incremented by 1

• The value held in the MDR is copied to the CIR

What occurs in the decode phase?

The contents of CIR are split into the opcode and the operand.

What occurs in the execute phase?

The decoded instruction is executed.

What occurs before the FDE cycle is carried out?

The program instructions need to be translated into machine code, and loaded from secondary storage to main memory.

What occurs after an FDE cycle has been completed?

The processor checks the status register to see if an exception or interrupt needs to be handled.

What does the program counter do in the FDE cycle?

Its contents are copied to the MAR, which is connected to the address bus. Once the data of that address has reached the MAR, it is incremented by 1.

What does the control unit do once the address of the instruction is on the address bus?

It does a memory read to allow the contents of the memory location to be transferred to the processor via the data bus.

What does the MDR do in the FDE cycle?

Holds the data from the address stored in the MAR, which is then transferred to the CIR after the PC is incremented.

Why are both the CIR and MDR needed?

It ensures the current instruction is kept safe so that the MDR can be used in the execute stage.

How is the MAR used in the FDE cycle?

This stores the address from the PC, which is then accessed by the MDR.