Sequential Circuits Lecture

Fill in the blank flashcards covering concepts related to sequential circuits, latches, flip-flops, and timing considerations.

RAM = __.

Random Access Memory; 8GB = 8 billion bytes

2.2 GHz = __.

2.2 billion clock pulses per second

Combinational circuits are circuits where the output values are __ from current inputs.

entirely dependent and predictable

Sequential circuits depend on __ of the circuit.

both the current inputs and the previous state

Sequential circuits allow the same input values to result in __ outputs.

different

Feedback in circuits helps in creating __.

sequential circuits

Gate Delay is described as __.

the length of time it takes for an input change to result in the corresponding output change

A feedback circuit example using AND shows that when A=0, QT+1 becomes __, regardless of QT.

0

In an OR gate feedback circuit example, if A=1, QT+1 becomes __, regardless of QT.

1

NAND and NOR gates with feedback have __ characteristics for storage devices.

more interesting

If A=0 in a NAND circuit, output Q will go to __.

1

If A=1 in a NAND circuit, Q's value can __.

change

The term 'unsteady state' in NAND refers to the inability to store __.

0 long

In NOR circuits, setting A=1 leads output Q to __.

0

Latches are formed when multiple gates of these types are __ together.

combined

In a SR latch, when S and R start as 1 and 0, R sets the output Q to __.

1

The state of a latch is considered __ when S and R are both 1.

forbidden

Unstable behaviour occurs when inputs go from 00 to __.

11

Clock signals are useful for indicating when the output may be __.

sampled

When clock signals are high, it indicates to update the __ of the latch.

output

Setup time refers to how long before the clock edge the input should be __.

stable

Hold time talks about how long after the clock edge the input needs to remain __.

stable

A clocked SR latch introduces an additional __ signal.

control input C

Clocking a SR latch prevents changes from reaching the second stage of __ gates.

NAND

The D latch design avoids __ problems.

indeterminate state

In a D latch, the value of D sets output __ whenever C is high.

Q low or high

If both S and R are high, the state of Q becomes __.

indeterminate

Synchronous reset in a flip-flop resets Q to 0 on the __ edge of the clock.

active

A shift register can store a multi-bit value such as a __.

16-bit integer

To load values all at once in a register, signals are fed into each __.

flip-flop

Load registers' values are maintained until __ changes.

the enable signal (EN) high