Sequential Circuits Lecture

Introduction to Computer Specs

• Computer Specs Terms:
  • RAM: Random Access Memory; 8GB = 8 billion bytes.
  • Processor Speed: 2.2 GHz = 2.2 billion clock pulses per second.
• Key questions:
  • How do you use circuits to store values?
  • What is the purpose of a clock signal?

Types of Circuits

• Combinational Circuits:
  • Outputs solely depend on current inputs.
• Sequential Circuits:
  • Outputs depend on both current inputs and the previous state.
  • Capable of changing internal states over time, allowing the same input values to yield different outputs.
  • Essential for memory storage and responding to changing inputs.

Feedback in Sequential Circuits

• Feedback Mechanism:
  • Feedback allows the output of a component to connect back to its input.
  • Results in circuits that can maintain states.
• Gate Delay:
  • Outputs in combinational circuits don't change instantaneously.
  • Gate Delay: Time required for an input change to result in an output change.

Feedback Exhibit: Circuits and Gates

AND Gate Feedback Example

• Shows how certain feedback leads to unhelpful states (e.g., QT and QT+1 can get stuck at zero).
• If A=0, QT+1 remains 0 regardless of the previous state.

OR Gate Feedback Example

• If A=1, QT+1 becomes 1, regardless of QT.
  -QT+1 also gets stuck at 1, limiting utility.

Important Feedback Gates: NAND & NOR

• NAND/NOR Feedback Characteristics:
  • Unlike AND/OR gates, NAND/NOR circuits can change based on inputs, allowing for storage functionality.

NAND Feedback Example

• Starts with A=0, which leads Q to 1 indefinitely if input remains unchanged.
• A=1 changes Q, but risk of unsteady outcomes.

NOR Feedback Example

• If set A=1 causes output Q=0, maintaining Q at 0 allows for change upon flipping A back.

Latches

• Combining multiple feedback gates results in latches, providing more stable behavior.

SR Latch Behavior

• SR Latch: Contains Set (S) and Reset (R) inputs.
  • Various sequences of inputs produce different output behaviors.
  • Allows circuit to remember signals when transitioning states.

Timing and Stability in SR Latch

• Outputs don’t change instantaneously: timing diagrams help understand potential unstable states (forbidden states) arising from input variations.

Clock Signals in Sequential Circuits

• Need for timing signal arises to inform circuits when outputs should be sampled (clock signals).
  • Clock Signals: Regular pulse signals indicating when to update latch outputs.

Clocked SR Latch

• Addition of NAND gates creates a clocked (gated) SR latch.
  • Control input (C) determines when inputs affect the latch.
  • On low clock, inputs don’t change latch state.

Addressing Asynchronous Behavior and Instability

• D Latch (Gated D-Latch):
  • Avoid indeterminate states by making inputs depend on a single signal D, controlling output based on clock status.

Flip-Flops: Handling Timing and Stability

Essential Concepts

• Edge-triggered Flip-Flops:
  • Change state only at the moment of a clock change, avoiding the flooding effects of latches.
  • Critical for accurate output without timing overlaps.

Various Flip-Flops

• T Flip-Flop: Toggles output when T input is high.
• JK Flip-Flop: Offers four behaviors based on J & K combinations, allowing for more sophisticated designs.

Sequential Circuit Design Considerations

• Design requires planning around flip-flops inputs for stability and accuracy.
• Timing considerations and layout complexity must be accounted for to prevent errors or unpredictable behavior.

Register Types: Shift and Load Registers

• Shift Registers:
  • Store multi-bit values sequentially based on clock cycles.
• Load Registers:
  • Enable loading all values at once using special D flip-flops, controlling the storage mechanism.

Summary

• Understanding sequential circuits and their components (like latches and flip-flops) is essential for designing stable, accurate digital systems.
• Clock signals and feedback mechanisms play crucial roles in timing and state management throughout various circuit designs.