CPU Structure & Instruction Flashcards

Instruction cycle

The instruction cycle is the process the CPU follows to fetch, decode, execute and store one instruction.

Fetch stage

In the fetch stage, the CPU retrieves the instruction from memory using the address stored in the Program Counter.

Decode Stage

In the decode stage, the Cpu interprets the fetched instruction and determines what action is required.

Execute stage

In the execute stage, the CPU performs the operation such as calculation, comparison or data movement.

Store ( write back ) stage

In the storage stage , the result of the execution is written back to a register or memory.

CPU components

Show the name components and functions of each.

Central Processing Unit ( CPU )

The CPU is the main component of a computer that processes instructions and controls system operations.

Arithmetic Logic Unit ( ALU )

The ALU performs arithmetic operations like addition and subtraction and logical operations like AND and OR

Control Unit ( CU )

The control Unit manages and coordinates the execution of instructions inside the CPU.

Register

A register is a small, fast memory inside the CPU used to temporarily store data and instructions

Program Counter

The Program Counter holds the address of the next instruction to be fetched from memory.

Instruction Register ( IR )

The instruction Register stores the instruction that is currently being executed.

Data Processing

The computer processes data to produce useful information

Data storage

The computer stores data either temporarily or permanently

Data movement

The computer moves data betwenn components for processing.

Control

The computer controls and manages all system operations.

RISC

RISC stands for Reduced Instruction Set Computer, which uses simple instructions for faster execution.

RISC Instruction

RISC uses simple and fixed - length instructions that are easy for the CPU to process.

RISC Execution Cycle

Most RISC instructions are designed to complete in one clock cycle.

RISC and Pipelining

RISC archicture supports efficient pipelining because of its simple and uniform instruction design