Computer System Architecture Pre-Final CS

*Computer Bus*

A communication pathway connecting two or more devices for data transfer, composed of conductors like wires or tracks.

*Address Bus*

A unidirectional bus that carries memory addresses from the processor to access data.

*Data Bus*

A bidirectional bus for transferring instructions and data between processor and other devices.

*Control Bus*

A bidirectional bus that sends control signals from the control unit and receives responses from devices.

*Serial*

Sends data bits one by one in sequence; used for long-distance and small data amounts.

*Parallel*

Sends multiple data bits simultaneously across multiple channels; faster than serial for short distances.

*Serial Bus*

Uses fewer cables, supports full-duplex, and is suited for long-distance communication. (Can transmit fewer data in faster clock cycle to achieve a higher data rate)

*Parallel Bus*

Uses more cables, supports half-duplex, and is used for short-distance high-speed communication. (Transmit several streams of data simultaneously along multiple channels)

*Synchronous*

Transfers data with a shared clock; no start/stop bits, offering faster and more reliable data transfer.

*Asynchronous Protocol*

Transfers data at any time using start/stop bits; timing varies, more flexible but slower.

*Bus Arbitration*

Process of determining which module gains control of the bus when multiple devices request access.

*Centralized Arbitration*

A central controller (bus arbiter) grants bus access, e.g., daisy-chaining.

*Distributed Arbitration*

All devices participate in deciding bus access; no central controller.

*Data Sharing (Bus Characteristic)*

Buses enable data transfer among peripherals.

*Addressing (Bus Characteristic)*

Uses address lines to send/receive data from specific locations.

*Power (Bus Characteristic)*

Buses provide power to connected peripherals.

*Timing (Bus Characteristic)*

Buses synchronize devices using a system clock.

*Chipset*

Facilitates communication between computer components; includes Northbridge and Southbridge.

*Northbridge*

Connects CPU to RAM; controls memory access via Front-Side Bus (FSB).

*Internal Bus (Front-Side Bus)*

Allows the processor to communicate with the system's central memory or the RAM.

*Southbridge*

Manages communication with I/O devices via Expansion Bus; also known as I/O Controller Hub (ICH).

*Expansion Bus*

This allow various motherboard components to communicate with one another.

*ISA (Industry Standard Architecture)*

Early bus with 8-bit data width, 20 address lines, and 8 MHz speed. (IBM introduced this for IBM pc using an 8088 microprocessor.)

*VESA (Video Electronics Standards Association)*

Enhanced bus for video performance; supports 132 Mbps. ( This bus is a standard interface between a computer and its expansion)

*AGP (Accelerated Graphics Port)*

High-speed video bus directly connected to CPU; up to 1.5 Gbps. (This is connected to the Cpu)

*PCI (Peripheral Component Interconnect)*

32/64-bit bus by Intel; supports up to 1 Gbps. (Intel Corporation developed this bus.)

*SCSI (Small Computer Systems Interface)*

ANSI-standard interface for fast peripheral communication.

*PCMCIA*

Standard bus for laptops with 68-pin plug-and-play cards.

*PCIe (PCI Express)*

Modern high-speed interface with multiple lanes (x1, x4, x8, x16, x32.). (x implies the number of lanes)

*USB (Universal Serial Bus)*

Standard plug-and-play interface supporting power and data for many devices.

*Input Peripheral*

This allows user input from the outside world to the computer.

*Output Peripheral*

This allows information output from the computer to the outside world.

*Input-Output Peripheral*

This allows information to be sent through input and output

*Behavior*

input, output, or storage purposes

*Partner*

human or machine interaction

*Data rate*

the amount of data transferred to or from the I/O device in a period. It is typically measured in bits per second

*Performance*

This refers to how fast the device is.

*Expandability*

This refers to the expansion of the I/O device.

*Dependability*

This refers to the capability of the range and control of an I/O device.

*Cost*

This refers to the cost (how cheap or expensive) of an I/O module or device.

*Size and Weight*

These refer to the dimensions of an I/O device.

*I/O Bandwidth*

Amount of data transferred between I/O and memory/CPU per unit time.

*I/O Latency*

Total time to complete an I/O operation; crucial for real-time systems.

*Programmed I/O*

CPU handles all I/O transfers and monitors devices directly.

*Interrupt Initiated I/O*

The interface determines when the peripheral is ready for data transfer, then it generates an interrupt

*Direct Memory Access (DMA)*

It is a technique of removing the CPU from the path and letting the peripheral device manage the memory buses directly to improve the speed of transfer.

*Buffer Chaining (DMA)*

Devices use linked memory buffers for continuous transfers.

*Operation Chaining (DMA)*

Devices execute a list of operations automatically, reducing CPU load.

*I/O Controller*

Interfaces between CPU and I/O device, handling control and simplifying operations.

*Interface translation*

It includes the connection, voltage supply, protocol enactor, clocking.

*Addressing*

It is able to process memory locations or addresses for the function of processing.

*Multiplexing*

It can combine multiple signals over the bus to reduce multiple bus usage.

*Buffering*

It gives data transfer a boost by preloading data into memory before processing.

*Error detection and correction*

It can detect errors and correction.

*Control of multiple steps*

This reduces CPU workload due to I/O controller being the one that processes I/O instructions

*Device Driver*

a small piece of software that tells the operating system and other software how to communicate with a piece of hardware