Digital Logic, Timing, CDC, and Verification: Key Concepts and Techniques

What is combinational logic?

Logic where outputs depend only on current inputs with no memory elements. Examples: adders, multiplexers, decoders, ALUs.

What is sequential logic?

Logic where outputs depend on current inputs AND past state, requiring storage elements like flip-flops. Examples: counters, shift registers, FSMs.

What causes unintentional latches in RTL?

Incomplete assignments in case or if statements, causing synthesis tools to infer latches.

How do you prevent unintentional latches?

Use always_comb for combinational logic, ensure all outputs are assigned on all paths.

What is setup time (Tsu)?

Minimum time BEFORE the clock edge that data must be stable for the flip-flop to capture it.

What causes setup violations?

Logic path is too slow, causing data to arrive too late before the clock edge.

How do you fix setup violations?

Optimize logic depth, add pipeline stages, increase clock period, or improve synthesis constraints.

What is hold time (Th)?

Minimum time AFTER the clock edge that data must remain stable for the flip-flop to capture it.

What causes hold violations?

Data changes too quickly after the clock edge, often due to short paths or excessive clock skew.

How do you fix hold violations?

Add buffers or delay elements; cannot be fixed by changing clock frequency.

Why are hold violations harder to fix than setup violations?

They are independent of clock frequency, requiring physical changes like adding buffers.

What is clock skew?

The difference in arrival time of the same clock edge at different flip-flops.

How does clock skew affect timing?

Positive skew can help setup but hurt hold; negative skew can help hold but hurt setup.

What is the timing equation for setup?

Tclk >= Tcq + Tlogic + Tsetup - Tskew.

What is metastability?

When a flip-flop samples a signal changing near the clock edge and enters an undefined state.

Why can't metastability be eliminated?

It is a physical limitation; we can only reduce the probability, not eliminate it.

What are the consequences of metastability?

Output may oscillate or settle to the wrong value, causing system failures.

How do you synchronize a single-bit signal crossing clock domains?

Use a 2-flip-flop synchronizer.

Why can't you use a 2-FF synchronizer for multi-bit buses?

Different bits may transition at different times, causing data corruption.

What are methods for synchronizing multi-bit buses across clock domains?

Async FIFO, handshake protocols, Gray code for counters, or MUX recirculation.

What is MTBF in the context of CDC?

Mean Time Between Failures - the average time between metastability events.

What are the main components of a UVM testbench environment?

Environment, Agent, Driver, Sequencer, Monitor, Scoreboard, Reference Model, Coverage Collector.

What is the role of the UVM Agent?

Contains driver, monitor, and sequencer; can be active or passive.

What does the UVM Driver do?

Receives transactions from the sequencer and converts them to pin-level activity.

What does the UVM Sequencer do?

Generates transaction sequences and arbitrates between multiple sequences.

What does the UVM Monitor do?

Observes DUT interface signals and converts pin-level activity back into transactions.

What does the UVM Scoreboard do?

Compares actual DUT outputs versus expected outputs and reports mismatches.

What is a reference model in verification?

A high-level behavioral model of the DUT that generates expected outputs.

What is directed testing?

Hand-crafted test cases targeting known scenarios and corner cases.

What is constrained random testing?

Automatically generates stimulus within specified constraints to explore the design space.

What is coverage-driven verification?

Methodology defining coverage goals, running tests, and analyzing coverage holes.

What is code coverage?

Structural coverage measuring what RTL code was executed.

Does 100% code coverage mean the design is bug-free?

No, it only shows what code executed, not whether it behaved correctly.

What is functional coverage?

Coverage measuring whether specification requirements were tested.

What should functional coverage include for a FIFO?

Empty/full transitions, fill levels, simultaneous read/write, overflow/underflow events.

What is the difference between immediate and concurrent assertions?

Immediate assertions check conditions at a single instant; concurrent assertions evaluate over time.

When do you use immediate assertions?

Inside procedural blocks to check conditions at specific execution points.

What are concurrent assertions?

Assertions that evaluate continuously over time using temporal logic.

When do you use concurrent assertions?

To specify temporal properties that span multiple clock cycles.

What does the |-> operator mean in SVA?

Overlapping implication - if the antecedent is true, the consequent must be true in the SAME cycle.

What does the |=> operator mean in SVA?

Non-overlapping implication - if the antecedent is true, the consequent must be true in the NEXT cycle.

What does ##N mean in SVA?

Delay operator - delays by exactly N clock cycles.

What is the difference between (valid |=> ready) and (valid |-> ##1 ready)?

They are equivalent; both check that if valid is true, ready must be true in the next cycle.

Write an assertion that read should never occur when FIFO is empty.

assert property (@(posedge clk) disable iff (!resetn) read_en |-> !empty);

Write an assertion that write should never occur when FIFO is full.

assert property (@(posedge clk) disable iff (!resetn) write_en |-> !full);

What is the difference between blocking (=) and non-blocking (<=) assignments?

Blocking executes sequentially immediately; non-blocking evaluates all RHS first, then assigns at end of timestep.

Why should you never mix blocking and non-blocking in the same always block?

Creates race conditions and simulation/synthesis mismatches.

How would you verify a FIFO?

Test basic read/write operations, full/empty conditions, simultaneous operations, overflow/underflow, and data integrity.

How do you handle X-propagation in verification?

Use 4-state simulators to reveal uninitialized registers and metastability paths.

What is constrained random verification?

Technique that generates random stimulus within specified constraints to explore design space.

Why use assertions in verification?

Detect bugs early, document design intent, and provide continuous checking during simulation.

What is a valid-ready handshake protocol?

Handshaking where source asserts valid with data, waits for destination to assert ready.

What tools are commonly used for design verification?

Simulators (VCS, Questa, Xcelium), debug tools (Verdi, DVE), formal verification tools.

What are the UVM run phases in order?

build, connect, end_of_elaboration, start_of_simulation, run, extract, check, report, final.

What is Gray code and when is it used in CDC?

Encoding where only one bit changes between consecutive values; used for counters crossing clock domains.

What is an async FIFO used for?

Synchronizing data streams between different clock domains.

How many FF stages are typically used in a synchronizer?

2 stages are standard for most applications.

What is the purpose of disable iff in assertions?

Disables the assertion when a condition is true, typically used for reset.

What is $stable() in SVA?

Checks that a signal's value is unchanged from the previous clock cycle.

What is $past() in SVA?

Returns the value of a signal from previous clock cycle(s).

What is toggle coverage?

Measures whether each signal toggled during simulation.

What is branch coverage?

Measures which branches of if/else and case statements were taken during simulation.

What is FSM coverage?

Measures which states were visited and which state transitions occurred.

What is cross coverage?

Coverage of combinations of multiple variables or events.

What is the clock-to-Q delay (Tcq)?

Time it takes for a flip-flop's output to change after the clock edge.

How does pipeline help with timing?

Breaks long combinational paths into shorter stages, reducing logic delay.

What is meant by 'coverage closure'?

Process of achieving target coverage goals by analyzing holes and refining tests.

What is the transaction flow in UVM?

Sequence → Sequencer → Driver → DUT → Monitor → Scoreboard.

What makes a good assertion?

Clear intent, checks one property, has appropriate severity, and includes proper handling.

What is the difference between an active and passive agent?

Active agent drives stimulus; passive agent only observes.

Why is data integrity important in FIFO verification?

Must verify FIFO ordering and that data read matches data written.

What CDC issues can occur with async FIFOs?

Metastability in pointer synchronizers and full/empty flag glitches.

What is a handshake protocol for CDC?

Source sets data and pulses request; destination captures data and sends acknowledge.

What questions should you ask the interviewer about their verification process?

What methodology, tools, and how do you verify critical interfaces?