fetch decode execute cycle notes (this is going to be fun)

step 1 of the fde cycle

step 1 of the fde cycle

The PC is loaded with 0 

step 2 of the fde cycle

The value from the PC (0) is copied to the MAR 

step 3 of the fde cycle

The data from the MAR (0) is sent across the address bus with the instruction to read the data sent across the control bus 

step 4 of the fde cycle

The data from that location in memory (0) is sent down the data bus to the MDR 

step 5 of the fde cycle

The PC is incremented by 1 

step 6 of the fde cycle

The data is sent from the MDR to the CIR where it is split into the opcode and operand 

step 7 of the fde cycle

This is sent to the CU to be decoded 

step 8 of the fde cycle

Which registers are being used here will depend on the instruction currently being executed 

• if a value is being inputted (INP) the ACC will store the value 

• If a value is being outputted (OUT) this will be the value currently in the ACC 

• If a value is loaded from RAM (LDA) this will be sent across the data bus from RAM (in the address location in the MAR) to the MDR 

• If a value is to be stored (STA) it will take the value from the ACC, send it to the MDR and then send it across the data bus to RAM (to the address location in the MAR) 

• If the LMC code is to branch (BRA/BRZ/BRP) the comparison will take place in the ALU