CMPEN 331 Exam 3 Spring 2025

End of Lec 21 + Lec 22-26

Direct Mapped Caching

Each memory block is mapped to exactly one block in the cache [(Block address) mod (Blocks in cache)]

Tag

The upper portion of an address that identifies a memory block

Validity bit

Verifies whether or not a block in a cache has data or not

Write-Through Caching

On a data-write hit, update the block in cache and memory

Write Buffer

A queue that holds data while it’s waiting to be written to memory

Write-Back Caching

On data-write hit, only update cache, then writing the modified block back to the memory when the block is replaced

Dirty bit

A bit used for each data cache block in write-back caching, to detect whether or not it requires a write-back to memory when evicted

Cache miss

A request for data in from the cache that cannot be filled as the data isn’t present in the cache; stalls CPU pipeline to grab data from memory

Compulsory miss

A cache miss that occurs when accessing new/empty data

Conflict miss

A cache miss that occurs when accessing a cache location mapped to by a different memory location

Capacity miss

A cache miss that occurs when the cache isn’t big enough to contain all the blocks needed by the program

Block size tradeoff

While larger block sizes take advantage of spatial locality, if the block size is too big compared to the cache size, the miss rate will go up, and miss penalty will also increase

Average Memory Access Time Formula

Hit time + (Memory penalty * Miss rate)

Handling a read cache miss

Stall the pipeline, fetch block from next level of memory, send memory to cache and processor

Handling a write cache miss (Write allocate)

Always write word into the cache updating both tag and data, no stalls

Handling a write cache miss (No write allocate)

Always write directly into the memory without cache allocation (invalidates that cache block)

Cache Size formula

Block count x (Block Size + Tag size + Valid bit size)

Tag Size formula

32 - log(block count x block size (in words) x word size (in bytes))

Block count

Bit count / word size / word count

DRAM Memory Organization

N rows by N column by M-bits; DRAM read/writes an entire M-bit at a time; each M-bit access requires a RAS/CAS cycle

RAS and CAS

Row Access Strobe and Column Access Strobe, two halves of DRAM addresses

Access time

Time between request and when word is read/written

Cycle time

Time between successive read/write requestsBa

Bandwidth

How much data can be supplied per unit time