Intro

Integrated Circuits consists of

Many Transistors on one chip

When the number of transistor on a IC increases it is known as

VLSI- Very Large Scale Integration

VLSI based on

CMOS chip

complementary metal oxide n-mos and p-mos semiconductors which are fast, cheap and low power transistors.

How do you build a simple CMOS chip

• CMOS transistor.

• Building logic gates from the CMOS transistors.

• Synchronous System Design.

• Transistor Layout and Fabrication.

• I/O and packaging.

What important factors are need in designing a CMOS Transistor

• Its design layout

• Fabrication Steps

Logic gates can be formed by

Connecting CMOS Transistors together

Why is Synchronous design important in the building of a CMOS chip and How is this done

To ensure that CMOS chip works efficiently because all memory elements will be updated simultaneously.

This is done by adding a global clock signal to all the memory elements in the chip.

Why is the packaging important in the building of CMOS Chips

• It protects the transistor from the outside environment

• it must have the ability to release the heat which is produced due to the switching of transistors

Delays in the CMOS chip is as a result of the

Packaging

50% of the delay of high performance computers is due to the packaging delay

Who invented the first transistor and where

Bardeen and Brattain in the research group of Schockley at Bell labs in 1947

They were awarded a Nobel Price

Describe the First Transistor

It consists of a triangle plastic wedge which is covered by a thin layer of gold

the tip is exposed to a germanium crystal which is placed on a metal layer called a base. The current flows in from the emitter on one side to the collector on the other side .

There is current amplification on the ___ side

Collector and this is how transistors work as amplifiers

The MOS Transistors where made to replace

Vacuum Tube Transistors which where large, not reliable and had high power

The disadvantage of using the first transistors is that

Manual Soldering of many components is very expensive

First Integrated Circuit be by

Jack Kilby from Texas Instruments 1958

The concept in building the First IC

Fabrication of passive and active components can be from the same material and they can be integrated in the same substrate

The first IC was a

Phase Shift Oscillator - its a linear circuit that aids in the generation of a sine wave

Moore’s Law

In 1965 Gordon Moore ( The cofounder of Intel) plotted the number of transistors on each chip to the year. He predicted that the number of transistors will be doubled every 26 months

The feature size of ICs

Shrink by 30% every 2-3 years

In an ideal case of a building a transistor

The length of the channel must be equal to the length of the polysilicon gate

The boundaries of the source and the drain must be equal to the boundaries of the polysilicon gate

What occurs during the fabrication process in the source and drain regions

The dopants diffuse laterally meaning that length of the drain and source will increase with a certain value

How is the gate capacitance calculated

The capacitance between the gate the channel and capacitance between the gate and drain and gate and source regions

The canonical (according to a set of rules) digital computing is

Binary Switching Transfer

The fundamental metrics for operation in Binary Switching Transfer

• Speed

• Energy

Field Scaling involves the

shrinking of the device linear dimensions by a x.

• The device linear dimensions are shrunk by a factor x

• the voltage also scaled as x to maintain a constant electric field in V/cm

Effect of Scaling on Speed

This shrinks the channel length and therefore the carriers travel for a shorter distance. MOSFET switching speed increases. The speed is scaled by 1/x

Energy transfer per binary switching operation is given as

C_devV²

The Effect of the Scaling on Energy

Since the voltage of the is scaled by x. The electrical field is needed to be kept constant .

The capacitance of the device is proportional to the area A=W⨉L/t_ox. since the area scales by a factor of x, the capacitance will scale by a factor of x

The energy will be scaled by x³

On scaling the transistor and the size is also reduced to a nanometer scale , certain channel effects become dominant which is

The leakage in the transistor

Scaling the Transistor

Lower energy per operation but more devices and faster speed

The power density of the devices increases by the year as the device scales this has made room for what innovations and because of

Rocket Nozzle and Nuclear Reactor.

To limit the amount of power being used the

Clock Speed was reduced to about 3GHz

Also using multicores and processors

The power density is limited and this is due to the __ this also limits the

temperature limitation and this limits the capability ( frequency and number of devices)

The delay in each wire is calculated by the

product of capacitance and resistance

The wire levels

• Intermediate

• Device

• Global

The levels of scaling

• Device

• I micrometer

• Chip

Scaling affects the

• Power Density

• Wire Delay

• Energy

• Speed

Clock Frequency values have saturated to a value due to

RC delays and Power Walls

64Kbit capacity/chip is the complexity of a

Page

The Kbit capacity/chip of the human DNA or Memory is the complexity o

64,000,000

Partitioning

Having a complex design or problem and breaking it into a smaller design or portion or task

Then after completing the smaller task combining them together to have the original complex design

The Hierarchical design in terms of complexity is

System Level → Module → Gate → Circuit → Device or Transistors

Types of Scaling

• Constant Field Scaling

• Constant Voltage Scaling

• Constant Voltage Scaling with velocity saturation

Constant Field Scaling

This reducing all the dimensions of the transistor and applied voltages with a scaling factor.

Since both the length and the voltage is scaled the electric field is constant → The energy E in the system is constant

Constant Voltage Scaling

By scaling the length, leakage levels in the transistor increases. This means that scaling the Voltage and decreasing its dimensions by the same scaling factor the same performance will not be gained.

To achieve a similar transistor performance ,Keep the voltage level the same