CPU Structure & Instruction

Central Processing Unit (CPU)

The "brain" of the computer that fetches, decodes, and executes instructions.

Control Unit (CU)

Coordinates the activities of the CPU, directs the flow of data, and decodes instructions.

Arithmetic Logic Unit (ALU)

Performs mathematical calculations (addition, subtraction) and logical operations (AND, OR, NOT).

Program Counter (PC)

Holds the memory address of the next instruction to be fetched.

Memory Address Register (MAR)

Holds the address in memory where data is to be fetched from or written to.

Memory Data Register (MDR

Temporarily holds the actual data or instruction fetched from or waiting to be sent to memory.

Current Instruction Register (CIR)

Holds the instruction currently being decoded and executed.

Accumulator (ACC)

A general-purpose register that stores the intermediate results of calculations performed by the ALU.

The Fetch Stage

The address in the PC is copied to the MAR; the instruction at that address is moved to the MDR, then to the CIR.

The Decode Stage

The Control Unit interprets the instruction in the CIR to determine what actions need to be performed.

The Execute Stage

The instruction is carried out (e.g., data is loaded, a calculation is performed in the ALU, or a result is stored).

Bus

Physical connections used to transfer data and signals between CPU components and memory.

Data Bus

Carries the actual data/instructions between the CPU and memory (Bi-directional).

Address Bus

Carries the location of the data being accessed (Unidirectional: CPU to Memory).

Control Bus

Carries command signals (like Read/Write) from the CU to other components.

Cache Memory

Extremely fast, small memory inside the CPU that stores frequently used data to speed up processing.

Von Neumann Architecture

A design where both program instructions and data are stored in the same shared memory.

Opcode vs. Operand

Opcode tells the CPU what to do

Operand tells the CPU what data to do it to

CISC (Complex Instruction Set Computing)

A CPU design where a single instruction can perform multiple low-level operations (like loading from memory, an arithmetic operation, and storing).

RISC (Reduced Instruction Set Computing)

A CPU design that uses a small, highly optimized set of simple instructions, usually resulting in faster execution per instruction.