Studied by 1 person
Arithmetic Logic Unit (ALU)
Performs arithmetic and logic operations
Central Processing Unit (CPU)
Made up of multiple components including:
Control Unit (CU)
Buses
Arithmetic Logic Unit (ALU)
Registers
Control Unit (CU)
Controls and coordinates the activities of the CPU by directing the flow of data between the CPU and other devices
Bus
A set of parallel wires connecting two or more components of the computer. Typically consists of 8, 16, 32 or 64 lines
Control Bus
Bi-directional bus that transmits commands, timing and specific status information between system components
Data Bus
Bi-directional bus that moves data and instructions between system components
Address Bus
Transmits the memory addresses of words that are used so data can be retrieved and sent back to the processor
Registers
Special memory cells that operate at very high speed. All arithmetic and logical/shift operations occur in registers
Program Counter (PC)
Holds the address of the next instruction to be executed
Current Instruction Register (CIR)
Holds the current instruction being executed, divided into operand and opcode
Memory Address Register (MAR)
Holds the address of the memory location from which data/instructions are fetched/written on
Memory Data Register (MDR)
Temporarily stores the data read from/written to memory
Fetch, Decode & Execute Cycle (FDE Cycle)
The sequence of operations that are involved in executing an instruction
Fetch Phase
Address of the next instruction is comping from the program counter (PC) to the memory address register (MAR)
The instruction held at the address is copied to the memory data register (MDR). The PC is then incremented by 1
The contents of the MDR are copied to the current instruction register (CIR)
Decode Phase
Instruction in the CIR is decoded & split into opcode + operand
Opcode = Tells the processor what needs to be done
Operand = Contains the data to be acted on
Factors that affect processor performance
Clock speed
Number of cores
Amount/type of cache memory
Clock speed
The amount of instructions completed per second. The faster the clock speed, the faster instructions will be executed
Number of cores
The more cores, the more instructions can be completed at once. However, some instructions are sequential
Amount/type of cache memory
Increases the amount of recent instructions that can be stored which prevents it from taking longer to retrieve
Pipelining
Stores and executes instructions from the processor in an orderly process
How does pipelining improve efficiency?
It allows multiple instructions to be executed simultaneously to reduce overall processing time
Three main types or architecture
Von Neumann
Harvard
Contemporary
Features of Von Neumann architecture
Uses a CISC processor
Shared memory space for instructions & data in the same format
One instruction at a time
A single control unit/processor follows a linear FDE cycle
Features of Harvard Architecture
Uses a RISC processor
Supports pipelining
Instructions & data are stored in separate memory units
Reading and writing data & fetching an instruction can be done simultaneously
Features of contemporary architecture
Modern computer architecture
Combines both Von Neumann & Harvard architecture
SIMD
Single instruction multiple data
Processor carries out a single instruction on multiple data items at the same time
MIMD
Multiple instructions multiple data
Multiple instructions are carried out on multiple data items across cores
