Phase-Locked Loops (PLL) - Vocabulary Flashcards

Vocabulary-style flashcards covering PLL components, detectors, dividers, VCO, loop filters, acquisition, modulation/demodulation, noise, and higher-order concepts from the lecture notes.

Phase-locked loop (PLL)

A closed-loop control system that synchronizes a VCO to an input signal using a phase detector, loop filter, and frequency divider so the VCO phase matches the input (φo = Nφi).

Phase detector

A device that outputs a voltage representing the phase difference between two input signals; commonly a multiplier (analog) or sequential detector (digital, e.g., RS flip-flop or phase/frequency detector).

Multiplier phase detector

An analog detector that multiplies two input signals; the DC output is proportional to cos(φ) near lock, with a linear region giving a phase gain Kp ≈ KV1V2/2 at φ ≈ π/2.

Sequential phase detector

A phase detector that responds to the relative timing of input edges; includes RS flip-flop detectors and phase/frequency detectors, offering wider capture ranges but varying noise performance.

Exclusive-OR phase detector

A phase detector using XOR with square-wave inputs; outputs a waveform whose DC component depends on phase difference; effective gain is Kp = 2KV1V2/π for sinusoidal inputs via mixed digital/analog operation.

Phase detector gain (Kp)

The slope of the phase detector output with respect to phase difference; near lock the gain determines how much VCO control voltage changes per radian of phase error.

RS flip-flop phase detector

A sequential detector that uses an SR flip-flop; has a linear range of 2π and provides a DC level that varies with phase difference, aiding wide capture but sensitive to noise.

Phase/Frequency Detector (PFD)

A detector built with two D-flip-flops and an AND gate; offers a 4π linear range, fast acquisition, and robust frequency/phase error indication for PLLs.

Dual-modulus prescaler

A high-frequency divider that alternates between dividing by P and P+1 depending on a modulus control, enabling large division ranges in synthesisers.

Fractional-N divider

A divider that effectively yields a fractional division by toggling between two integers; provides fine frequency steps but introduces reference-sideband modulation that must be managed.

VCO (Voltage-Controlled Oscillator)

An oscillator whose output frequency is controlled by a tuning voltage; Kv = dωo/dVt; tuning curves can be nonlinear and influence loop dynamics and phase noise.

VCO gain (Kv)

The sensitivity of the VCO frequency to the tuning voltage; units are rad/s per volt and affect the loop’s natural frequency and stability.

Loop filter

The filter in the PLL that shapes the closed-loop response; often an active network (op-amp) providing integration and damping to form a second- or higher-order loop.

Second order Type II PLL

A PLL with a second-order loop filter that yields a phase-locked response with a zero and two poles, characterized by natural frequency ωn and damping factor ζ.

Loop natural frequency (ωn)

The characteristic frequency of the PLL’s closed-loop response (higher ωn means faster tracking but potentially more reference-sideband noise); in the notes ωn is related to the product KpKv and chosen resistor/capacitor values.

Damping factor (ζ)

A dimensionless parameter determining the transient response; typical values range 0.5–1, with ζ = 0.707 giving a Butterworth-like response and good trade-offs between speed and overshoot.

Phase margin

Stability margin defined as the difference in phase between the loop gain’s phase and -180° at the unity-gain frequency; larger margin indicates more robust stability.

Noise bandwidth (BL)

An effective rectangular bandwidth that quantifies how much input noise passes through the loop; for a second-order Type II PLL, BL ≈ ωn^2(ζ + 1/(4ζ)).

Phase jitter

Random fluctuations in the VCO phase caused by input noise within the loop’s bandwidth; increases with loop bandwidth and decreases with higher input SNR.

Lock-in range

The initial frequency offset range over which the PLL can acquire lock without cycle slips when using a multiplier-type detector.

Pull-in range

The broader frequency offset range from which the PLL can acquire lock, possibly with cycle slips; typically larger than the lock-in range and depends on loop gain and filter.

Hold-in range

The frequency range within which the PLL can remain locked once acquisition has occurred, determined by the DC loop gain.

Aided acquisition

Acquisition assistance methods (e.g., VCO frequency sweep, auxiliary signals, or detectors) used to help the loop lock when free-running pull-in is slow or unlikely.

Two-point modulation

A modulation scheme combining phase and frequency modulation by injecting PM into baseband and FM into the loop, achieving a flat overall response across modulation frequencies.

Demodulation PLLs

PLL configurations used for demodulation (PM or FM) rather than synthesis; the phase detector’s operating range and loop bandwidth determine demodulation performance.

Costas loop

A Costas-type demodulator for BPSK (or QPSK) that uses a modulo-π phase detector and quadrature branches to achieve coherent demodulation and improved SNR at low publicly.

Direct Digital Synthesis (DDS)

An alternative to PLLs that computes the digital sine wave directly and then converts it to analogue; enables high resolution and fast switching, often noisier than PLL-based synthesis.

Harmonic locking

PLL locking to an odd harmonic or sub-harmonic of the input signal when using multiplier detectors; a design concern that can complicate lock.

Frequency translation loop

A PLL variant where a translation in the VCO-divider path yields fout = fin ± Nfref, enabling certain synthesis or receiver architectures with caution against latch-up.

Third-order Type II loop filter

An extended loop filter adding an extra pole (and possibly a zero) to improve high-frequency rejection and reduce reference sidebands while increasing design sensitivity.

Two-point FM/PM modulation (Equations 58-60)

Describes how PM and FM modulation combine in higher-order Type II PLLs to yield flat PM/FM responses around the loop’s natural frequency.

Reference sidebands

Unwanted sidebands at the reference frequency produced by the loop’s modulation; higher-order loops and proper filtering reduce these sidebands.

Phase/frequency detector linear range

RS detector: 2π; PFD: 4π; a larger linear range helps with acquisition and reduces dead zones compared to simple multiplier detectors.

Two-phase modulation and SNR impact (Costas/Costas-like)

Demodulation systems that use quadrature or coherent detection to maintain performance even under carrier modulation, though performance degrades with very low SNR.