COMP1860 Lecture 9.2 Notes: Parallel Processing

Flashcards covering symmetric multiprocessing, cache coherence, multithreading, clusters, NUMA, and cloud computing.

Symmetric Multiprocessing (SMP)

Enhances processing power by using multiple processors under a unified OS.

SMP Key Characteristics

Includes multiple processors of similar capability, shared main memory and I/O facilities, equal memory access time for all processors, symmetric architecture where all processors perform the same tasks, and a single OS to manage all processors.

Time-Shared Bus

A simple multiprocessor interconnection mechanism using shared control, address, and data lines.

Addressing

Identifies data sources and destinations on a bus.

Arbitration

Resolves competing bus access requests.

Time-Sharing

Allows one module to control the bus at a time.

Cache Coherence Problem

Occurs when one processor updates a value, and others must be notified to prevent inconsistencies.

MESI Protocol

A cache coherence protocol widely used in x86 architectures, combining hardware and software strategies.

Write-back Policy

Updates only the cache; main memory is updated when the cache evicts the data.

Write-through Policy

Writes update both the cache and main memory simultaneously.

Directory Protocols

Centralized tracking of cache states.

Snoopy Protocols

Each cache monitors memory transactions.

Write-Invalidate Protocol

A write operation invalidates copies in other caches before proceeding, ensuring only one writer at a time.

Write-Update Protocol

Updates are broadcasted so all caches holding the line can modify it, allowing multiple readers and writers.

MESI Cache Line States

Modified, Exclusive, Shared, and Invalid, which indicate the status of a cache line.

Interleaved Multithreading (Fine-Grained)

The processor handles multiple thread contexts simultaneously, switching to a different thread at each clock cycle.

Blocked Multithreading (Coarse-Grained)

Executes instructions from a single thread continuously until a long-latency event occurs, then switches to another thread.

Simultaneous Multithreading (SMT)

Allows multiple threads to issue instructions in the same cycle, maximizing CPU resource utilization.

Chip Multiprocessing (Multicore)

Multiple cores are integrated on a single chip, each executing its own thread independently.

Clustering

An alternative to SMP, consisting of multiple interconnected computers (nodes) working together.

NUMA (Nonuniform Memory Access)

Memory access time depends on which region is accessed; different processors experience different memory latencies.

CC-NUMA (Cache-Coherent NUMA)

A NUMA system that maintains cache coherence among processors.

Cloud Computing

Delivers flexible, on-demand compute resources at scale.