A-Level OCR Computer Science (1.1.1)

CPU

Central Processing Unit

ALU

Arithmetic Logic Unit

CU

Control Unit

PC (CPU)

Program Counter

ACC

Accumulator

MAR

Memory Address Register

MDR

Memory Data Register

CIR

Current Instruction Register

Define CPU

The main processor in a computer system handling data and instructions.

Define ALU

A circuit that performs mathematical and logical (comparative) operations.

Define CU

A component that handles data flow with 'control signals'. It also decodes instructions in the FDE cycle.

Define PC (CPU)

A REGISTER which holds the address of the next instruction to be executed.

Define ACC

A REGISTER which stores the results of calculations processed by the ALU.

Define MAR

A REGISTER which stores the address of the memory location currently in use.

Define MDR

A REGISTER which stores the instructions or data to be executed.

Define CIR

A REGISTER which stores the instruction while it is being decoded.

Define Register

A location where data can be stored.

Give the names of all 5 CPU registers

- PC (Program Counter)

- MAR (Memory Address Register)

- MDR (Memory Data Register)

- CIR (Current Instruction Register)

- ACC (Accumulator)

Define Bus

Wires that transmit data between the components in the CPU.

Give the names of the 3 CPU buses

- Data Bus

- Address Bus

- Control Bus

Define Data Bus

A bus on a HALF-DUPLEX pathway that transmits DATA between the CPU and memory.

Define Address Bus

A bus on a SIMPLEX pathway that transmits MEMORY LOCATION ADDRESSES between the CPU and memory.

Define Control Bus

A bus on a DUPLEX pathway that transmits SIGNALS between all components.

Define Simplex Pathway

A pathway that transmits data in only one direction.

Define Half-Duplex Pathway

A pathway that transmits data in both directions but not simultaneously.

Define Duplex Pathway

A pathway that transmits data in both directions simultaneously.

Define Assembly Language

A low level programming language designed for a specific type of processor. Converted into machine code with an assembler.

Assembly: LDA

Load - transfers a number from RAM to the ACC.

Assembly: STA

Store - transfers a number from the ACC to RAM.

Assembly: ADD

Add - adds the ACC contents to the contents of a specified RAM address.

Assembly: SUB

Subtract

Assembly: INP

Input - inputs a value and stores it in the ACC.

Assembly: OUT

Output - outputs the contents of the ACC.

Assembly: HLT

End (Halt) - stops the processor/process.

Assembly: BRZ

Branch if Zero - if the ACC = 0, the PC is set to the given address.

Assembly: BRP

Branch if Zero or Positive - if the ACC = 0+, the PC is set to the given address.

Assembly: BRA

Branch Always - set the contents of the ACC to the given address.

Assembly: DAT

Data Definition - loads the given value into the next available slot or can declare variables.

Define Opcode

The part of an assembly instruction that defines the operation (e.g. LDA, STA, HLT, ADD, etc).

Define Operand

The data that is being manipulated by the opcode. Written in HEXADECIMAL.

FDE Cycle

Fetch-Decode-Execute Cycle.

What are the 4 steps of FETCH in the FDE cycle?

1. The address in the PC is copied to the MAR.

2. The PC is incremented.

3. A fetch signal is sent along the Control Bus by the CU to memory. The Address in the MAR is sent to memory along the Address Bus. The value in memory returns to the CPU along the Data Bus to the MDR.

4. The value in the MDR is copied to the CIR.

What are the 2 steps of DECODE in the FDE cycle?

1. The contents of the CIR are sent to the CU for decoding.

2. The addressing is identified.

- Direct Address: load to MAR and retrieve contents.

- Indexed Address: add contents of the index register to the address and copy it to the MAR. Retrieve the contents.

What are the 2 possible steps of EXECUTE in the FDE cycle?

If the instruction is a jump: load the address operand into the PC and copy the address in the CIR to the PC

Otherwise: execute the instructions.

List the 4 factors affecting CPU performance

- Clock Speed

- Cache Memory

- Number of Cores

- Pipelining

What is clock speed?

The amount of FDE cycles a CPU can perform every second (measure in hertz).

What is cache memory?

Memory that temporarily stores data that is faster to access than RAM.

What is a core?

An individual processor.

What is multicore processing?

Using multiple cores to handle different tasks simultaneously (used in multitasking).

What is pipelining?

A process where next instruction for a process is fetched while the current instruction is being decoded.

List 4 additional factors that affect CPU performance

- Temperature

- Multithreading

- Bus width

- Register size

Von Neumann Architecture:

- Buses

- Instruction order

- Data/instruction storage

- simultaneous access

- clock cycles for instructions

- Data, address, control

- Sequential

- Data and instructions in same memory unit

- Cannot fetch multiple instructions simultaneously ("Von Neumann Bottleneck")

- Two clock cycles

Harvard Architecture:

- Buses

- Instruction order

- Data/instruction storage

- simultaneous access

- clock cycles for instructions

- Data, address, control, instruction

- Sequential

- Data and instructions are separate

- Reading and memory access simultaneous

- Two clock cycles (1 with pipelining)

Contemporary Architecture:

- Buses

- Instruction order

- Data/instruction storage

- simultaneous access

- clock cycles for instructions

- Data, address, control, instruction

- Sequential

- Relaxed separation of data and instructions

- Reading and memory access simultaneous

- Two clock cycles (1 with pipelining)