Sequential Logic Circuits and Memory Elements

Flashcards covering key concepts from Unit 3: Sequential Logic Circuits, including Latches, Flip-Flops, Counters, Shift Registers, Clock Signals, and Master-Slave configurations.

How does a sequential circuit differ from a combinational circuit regarding output determination?

A combinational circuit produces outputs based on current inputs only, whereas a sequential circuit produces outputs based on both current inputs and the previous state stored in memory elements.

What is the primary distinction between a latch and a flip-flop in terms of clock sensitivity?

A latch is level-triggered and responds during the entire active level of an enable signal, whereas a flip-flop is edge-triggered and changes state only on a rising or falling clock transition.

What mathematical relationship defines clock frequency ($f$) relative to the time period ($T$)?

$$f = \frac{1}{T}$$

What defines a positive edge clock trigger?

The circuit triggers on the rising transition of the clock signal, transitioning from low ($0$) to high ($1$).

In an S-R latch built using NAND gates, which input combination results in an invalid or prohibited state?

Inputs $S = 0$ and $R = 0$, because this input forces both outputs $Q$ and $\overline{Q}$ to $1$, violating the condition that outputs must be complementary.

In an S-R latch constructed with NOR gates, what input condition leads to the prohibited state?

Inputs $S = 1$ and $R = 1$.

What is the characteristic equation for an SR flip-flop?

$$Q_{n+1} = S + \overline{R}Q_n$$

What specific drawback of the SR flip-flop was the JK flip-flop designed to solve?

It resolves the indeterminate state or race condition that occurs in an SR flip-flop when both inputs are $1$.

What is the next state $Q(n+1)$ of a JK flip-flop when inputs are $J = 1$ and $K = 1$ upon receiving a clock trigger?

$\overline{Q}_n$ (Toggle mode).

What is the characteristic equation of a D flip-flop?

$$Q_{n+1} = D$$

How is a T flip-flop formed from a JK flip-flop?

By connecting both inputs together such that $J = K = T$.

What is the primary function of an excitation table in sequential logic circuit design?

It shows the required flip-flop inputs needed to cause a transition from a given present state $Q_n$ to a desired next state $Q_{n+1}$.

What are Preset ($PR$) and Clear ($CLR$) inputs in flip-flops, and what is their priority level?

They are asynchronous inputs used to directly force the flip-flop state to $1$ (Preset) or $0$ (Clear) regardless of the clock signal, and they have the highest priority.

Why are synchronous counters faster than asynchronous (ripple) counters?

In synchronous counters, all flip-flops are clocked simultaneously by an external clock, avoiding accumulated propagation delays across cascading flip-flops.

For a digital counter constructed using $n$ flip-flops, how many total states exist and what is the maximum count value?

It has $2^n$ possible states and a maximum count of $2^n - 1$.

In a negative-edge triggered asynchronous ripple UP counter, where is the clock input of each subsequent flip-flop connected?

It is connected to the normal output $Q$ of the preceding flip-flop.

How many clock pulses are needed to load and read out an $n$--bit word in a Serial-In Serial-Out (SISO) shift register?

It requires $n$ clock pulses to load data and $n - 1$ clock pulses to read data out, making a total of $2n - 1$ clock pulses.

In a Universal Shift Register, what operation is executed when control inputs $S_1 S_0 = 11$?

Parallel load.

Under what conditions does the Race Around Condition occur in a JK flip-flop?

It occurs when $J = 1$ and $K = 1$ while the clock pulse width ($t_p$) is greater than the propagation delay (speed of operation) of the flip-flop.

How does a Master-Slave JK flip-flop eliminate the race-around condition?

It cascades two latches with inverted clock signals so that the Master latch accepts input data while the clock is high, and transfers data to the Slave output only on the falling edge of the clock signal.

What internal components are contained inside an IC 7476 chip?

Two dual JK flip-flops with individual Preset and Clear inputs.

Identify the sequential circuit component architecture shown in this block diagram:

A general sequential circuit where the memory element stores binary state information and feeds current state variables back into the combinational logic.

Which IC pinout layout is illustrated in this diagram?

IC 7476 Dual JK Flip-Flop pin configuration with active-low Preset and Clear terminals.

What flip-flop circuit configuration is shown in this logic diagram?

Master-Slave JK Flip-Flop circuit consisting of a master latch and a slave latch.