Lab 5: Design of a Two Stage CMOS Operational Amplifier

This set of vocabulary flashcards covers the design specifications, model parameters, and simulation techniques for a Two Stage CMOS Op-Amp based on Lab 5 of EEE466.

Two Stage CMOS Operational Amplifier

An un-buffered amplifier circuit with an n-channel input pair designed to study large signal dc and small signal ac characteristics using Cadence Virtuoso.

$A_v$ (Voltage Gain)

The specified gain for the Op-Amp design which must be greater than $5000\,V/V$.

GB (Gain Bandwidth)

A specification for the Op-Amp set at $5\,MHz$ to determine small signal performance.

SR (Slew Rate)

The rate of change of output voltage, specified as $> 10\,V/\mu s$.

$V_{out}$ range

The specified output voltage swing for the Op-Amp, defined as $\pm 2\,V$.

ICMR (Input Common Mode Range)

The range of common-mode input voltages over which the amplifier operates properly, specified as $-1$ to $2\,V$.

$P_{diss}$ (Power Dissipation)

The maximum allowed power consumption for the design, specified as $\le 2\,mW$.

Section TNTP

The typical NMOS and typical PMOS section of the model file used for simulation in the Spectre environment.

$VTO$ (Zero-bias threshold voltage)

A level 2 model parameter specified as $0.775$ for nmos4 and $-0.75$ for pmos4.

$tox$ (Gate oxide thickness)

A model parameter specified as $400 \times 10^{-10}\,m$ for both NMOS and PMOS transistors.

$C_c$ (Compensation capacitor)

A component calculated in the PRE-LAB design phase to ensure stability in the two-stage Op-Amp.

Transfer characteristics

A dc analysis used to find the output offset voltage and input offset voltage by sweeping the $V+$ terminal voltage.

Dominant pole

The primary pole of the amplifier frequency response, determined from the magnitude versus frequency plot.

Phase Margin

A stability metric determined from the frequency response using the Virtuoso Visualization and Analysis Calculator.

CMRR (Common Mode Rejection Ratio)

A measure of the amplifier's ability to reject common-mode signals, simulated using a unity gain configuration where $\frac{V_{out}}{V_{cm}} = \frac{1}{CMRR}$.

PSRR+ (Positive Power Supply Rejection Ratio)

The ratio of the change in positive supply voltage to the change in output voltage, defined as $\frac{\Delta V_{DD}}{\Delta V_{out}}$.

PSRR- (Negative Power Supply Rejection Ratio)

The ratio of the change in negative supply voltage to the change in output voltage, defined as $\frac{\Delta V_{SS}}{\Delta V_{out}}$.

xf analysis

A simulation type in Spectre used to determine transfer functions from $V_{DD}$ and $V_{SS}$ to the output to calculate PSRR.

Philips E. Allen and Douglas R. Holberg

The authors of the textbook 'CMOS Analog Circuit Design, Second Edition' used as the reference for the design procedures in this lab.