WEEKS 6-10

Interconnect

Wires in integrated circuits that set the size of components and are as important as transistors for speed, power, and noise.

Pitch

The total width of a wire plus the space between wires.

Aspect Ratio (AR)

The ratio of thickness to width of a wire; critical for maintaining sheet resistances in deep submicron processes.

Resistivity

The measure of how strongly a material opposes the flow of electric current, expressed in ohm-centimeters (\Omega*m).

Sheet Resistance

Resistance of a thin film or layer of material given in \Omega per square (\Omega/\square); crucial for analyzing wire performance.

Capacitance

The ability of a wire or component to store an electric charge; typically increases with the surface area and decreases with greater distance.

Crosstalk

Interference caused by capacitive coupling between wires, leading to increased noise and delay in non-switching wires.

Dual Damascene

An advanced metallization process used in IC fabrication where metal is simultaneously patterned and formed using two etching steps.

Electromigration

The phenomenon where atoms in a conductor migrate due to high current density, leading to reliability issues.

Low-k Dielectrics

Materials with low dielectric constants used to reduce capacitance and improve performance in interconnects.

IR Drop

Voltage drop across a power distribution network due to resistive losses, which can affect the performance of ICs.

Repeaters

Devices used to boost signal strength in long interconnects by breaking them into shorter segments.

Metal Layer Cross Section

The structural arrangement of metal layers in an integrated circuit, impacting wire resistance and capacitance.

Niobium

A metal used for wiring in advanced CMOS processes due to its favorable electrical characteristics.

Transistor Gate

The component of a transistor that controls the flow of current based on signal inputs; its design significantly affects circuit performance.

Datapath Design

The architecture encompassing various components such as comparators, shifters, adders, and multipliers for processing data.

Comparator

A digital circuit that compares two values and outputs the result of that comparison.

Shifter

A circuit that shifts the bits of a binary number left or right.

Adder

A digital circuit that performs addition of numbers.

Multiplier

A hardware component used to multiply two numbers.

I-cache (Instruction Cache)

Memory used to store instructions that the CPU will execute.

Predecoder

A circuit that prepares signals for further processing by dividing them into smaller parts.

Register

A small amount of storage available in a CPU for quick data access.

Branch Prediction

The ability of a CPU to guess which way a branch (like an if statement) will go before it is known for sure.

ALU (Arithmetic Logic Unit)

The part of a CPU that performs arithmetic and logical operations.

Carry Save Addition (CSA)

An adder that produces outputs to minimize delays by keeping results in a carry-save format.

Barrel Shifter

A circuit that shifts bits around using a rotate operation.

Booth's Algorithm

An algorithm for multiplying binary integers in signed and unsigned form.

Funnel Shifter

A shifter that can perform various types of bit shifts, including logical, arithmetic, and rotating shifts.

Logical Shift Right (LSR)

Shifts bits right, filling with zeros from the left.

Logical Shift Left (LSL)

Shifts bits left, filling with zeros from the right.

Arithmetic Shift Right (ASR)

Shifts bits right while preserving the sign bit.

Magnitude Comparator

A component that compares the sizes of two binary numbers.

1's Detector

A circuit that detects if there is at least one '1' in the input.

0's Detector

A circuit that detects if all inputs are zero.

Equality Comparator

A circuit that checks if two binary numbers are equal.

Signed vs. Unsigned Comparison

Refers to the complexity of comparing numbers based on their representation in binary regarding their sign.

Combinational Circuit

A type of circuit where the output is a direct function of the current inputs without memory elements.

NAND Gate

A digital logic gate that produces a low output (0) only if all its inputs are high (1).

MUX (Multiplexer)

A device that selects one of many inputs and forwards the selected input to a single output.

VHDL

VHSIC Hardware Description Language, used to describe the behavior and structure of electronic systems.

Elmore Delay

A delay measure that considers the resistive and capacitive effects in a network, helping to estimate signal propagation time.

Logical Effort

The measure of how effectively a gate can produce output current in relation to its input capacitance.

Asymmetric Gates

Gates that are designed with unequal input sizes to optimize performance based on input criticality.

Parasitic Delay

Delay introduced by the internal capacitance of a gate, which affects signal propagation time.

Electrical Effort

The ratio of output capacitance to input capacitance, influencing how much load a gate can drive.

Skewed Gates

Gates that favor one output transition over the other to improve performance, often by adjusting transistor sizes.

P/N Ratio

The ratio of PMOS to NMOS widths that affects the rise and fall times, influencing circuit speed and power.

Compound Gate

A gate design that incorporates multiple functions or operations within a single gate configuration.

Critical Path

The longest path through a circuit, determining the minimum time required for all outputs to stabilize after a change in input.

Branching Effort

The effort associated with distributing the signal among branching paths in a circuit, affecting timing and delay.

Sizing Analysis

The process of determining the optimal dimensions of transistors to achieve desired circuit performance.

Driver Sizing

Adjusting the sizes of output drivers in a circuit to optimize speed and minimize delay.

Timing Analysis

The process of assessing the timing behavior of signals in digital circuits, focusing on delays and synchronization.

Circuit Optimization

Modifications made to enhance circuit performance, often through reducing component counts or improving speed.

Clock Skew

The difference in arrival times of the clock signal at different components due to manufacturing variances and signal propagation delays.

Clock Jitter

Variability in the timing of clock edges due to noise and variations in power supply, leading to uncertainty in signal timing.

Flip-Flop

An edge-triggered device that samples and captures data on the rising edge of a clock signal.

Latch

A level-sensitive device that follows the input signal as long as the enable signal is active.

Setup Time (Tsu)

The minimum time before the clock edge that the data input must be stable.

Hold Time (Thold)

The minimum time after the clock edge that the data input must remain stable.

Propagation Delay (tpd)

The time between a change at the input and the corresponding change at the output.

Contamination Delay (tcd)

The minimum time it takes for an output to start changing after the input changes.

Phase Locked Loop (PLL)

A technology used to synchronize clock phases with a reference, potentially multiplying the frequency.

Delay Locked Loop (DLL)

A technology that introduces specific delays to synchronize clock signals across different systems.

Metastability

A state where a flip-flop output is neither in a clear high nor low state, occurring during data transitions.

Clock Distribution

The mechanism that distributes the clock signal to various components to ensure synchronous operations.

Separation of Cycles

The ability to distinguish between different operational cycles in a synchronous system.

Synchronous System

A system where operations are coordinated by a clock signal to ensure proper timing and sequencing.

Clock Gating

A technique to reduce power consumption by disabling the clock to portions of the circuit when not needed.

Useful Skew

Clock skew that can be exploited to reduce timing violations and improve setup and hold times.

Sequential Logic

Logic circuits in which the output depends on the current and previous inputs, introducing memory elements like latches and flip-flops.

Half Adder

A digital circuit that computes the addition of two bits, producing a sum and a carry.

Full Adder

A circuit that adds three bits, producing a sum and a carry output.

Carry-out (Cout)

The output carry from a binary addition of bits that is passed to the next higher bit position.

Propagation

The phenomenon where a carry is passed through each stage of an adder.

Majority Gate (MAJ)

A logic gate that outputs the majority value from its inputs, used in full adder designs.

Carry Generate (G)

A condition where Cout is 1 independent of Cin, represented by G = A \bullet B.

Carry Propagate (P)

The condition where Cout follows the input carry Cin, represented by P = A \oplus B.

Carry Kill (K)

A condition where Cout is 0 independent of Cin, represented by K = \sim A \bullet \sim B.

Ripple Carry Adder

An adder that cascades individual full adders, where each adder's carry-out is connected to the next adder's carry-in.

Carry-Lookahead Adder (CLA)

An adder that computes carry outputs in parallel, enhancing speed compared to ripple carry adders.

Tree Adder

An adder structure that reduces delay by using recursive lookahead strategies to compute carries.

Manchester Carry-Skip Adder

A variant of carry-skip adders that uses dynamic logic to allow carry generation to skip over multiple bits.

Factor S

The expression used to derive the sum in a full adder design, such as S = A \oplus B \oplus Cin.

Complementary Pass Transistor Logic (CPL)

A logic style that uses pass transistors for faster designs but at the cost of more area.

N-bit Carry Propagate Adder (CPA)

An adder where each sum bit depends on all previous carries, often used in parallel computation of carries.