Computer Architecture & Organization – Exam Review Vocabulary

This set of vocabulary flashcards covers major concepts, components, and techniques from computer architecture and organization, including processor design, memory hierarchy, I/O, parallelism, logic design, and storage systems.

Von Neumann Architecture

Computing model in which program instructions and data share one read-write memory and travel over the same bus.

Computer Architecture

Attributes of a computing system visible to a programmer (instruction set, data types, addressing modes, etc.).

Computer Organization

Hardware implementation details that realize the architecture (signal pathways, control signals, memory technology, etc.).

Four Basic Computer Functions

Data processing, data storage, data movement, and control.

Data Movement

Function that moves data among components or in/out of memory via buses and I/O paths.

First-Generation Computers

Machines that used vacuum tubes for logic and memory.

Second-Generation Computers

Systems built with discrete transistors.

Third-Generation Computers

Computers that employed small-scale and medium-scale integrated circuits.

Fourth-Generation Computers

Systems built with large-scale integrated circuits and microprocessors.

System Clock

Electronic circuit that generates a periodic pulse to synchronize processor operations.

Clock Speed

Number of clock cycles per second, usually expressed in hertz (Hz).

Clock Tick

Single pulse of the system clock signalling one basic timing interval.

Memory Address Register (MAR)

CPU register that holds the address of the memory location to be accessed.

Memory Buffer Register (MBR) / MDR

Register that temporarily holds data read from or written to memory.

Program Counter (PC)

Register containing the address of the next instruction to fetch.

Instruction Register (IR)

Register that holds the currently executing instruction.

Two’s Complement

Binary representation that allows straightforward signed integer arithmetic; leading bit is the sign.

Synchronous Bus

Bus protocol whose events are coordinated by a common clock signal.

Cache Memory

Small, fast memory that stores frequently accessed data to reduce average access time to main memory.

Set-Associative Cache

Cache organization in which each block can map to any line within a small set.

Cache Tag

Field stored with each cache line identifying the corresponding main-memory block.

API (Application Programming Interface)

Set of high-level routines and protocols allowing programs to request services from software libraries or OS components.

Process State – Running

OS state indicating a process currently executing on the CPU.

Process State – Ready

State in which a process is prepared to run but waiting for CPU time.

Paging

Memory-management scheme that maps fixed-size virtual pages to physical frames.

Translation Lookaside Buffer (TLB)

Cache that stores recent virtual-to-physical address translations.

Boolean AND

Logical operation yielding true only if all operands are true.

Boolean OR

Logical operation yielding true if at least one operand is true.

Boolean NOT

Unary operation that inverts the value of its operand.

Boolean XOR

Operation yielding true if operands differ.

Boolean NAND

Operation yielding false only when all operands are true.

General-Purpose Register (GPR)

CPU register that can hold either data or an address as assigned by the programmer.

Direct Addressing Mode

Addressing mode where the instruction contains the explicit memory address of the operand.

Register Indirect Addressing

Mode where an instruction refers to a register whose contents are the memory address of the operand.

Displacement (Indexed) Addressing

Effective address computed by adding a constant to a register value.

Relative Addressing

Effective address is calculated by adding an offset to the current PC.

Autoindexing (Post-increment)

Addressing mode that uses a register as a pointer then automatically increments it.

PDP-8

12-bit minicomputer famous for single accumulator architecture.

Arithmetic and Logic Unit (ALU)

Processor component that performs arithmetic and bit-wise logical operations.

Control Unit (CU)

CPU part that directs data flow, decodes instructions, and issues control signals.

Control & Status Registers

Privileged CPU registers used by the OS to control processor operation and record status.

Instruction Pipelining

Overlapping execution of successive instructions to increase throughput.

CISC (Complex Instruction Set Computer)

Architecture featuring many variable-length, multi-cycle instructions with numerous addressing modes.

RISC (Reduced Instruction Set Computer)

Architecture emphasizing simple, fixed-length instructions and pipeline efficiency.

Register File

Array of CPU registers accessible within a single clock cycle.

Instruction-Level Parallelism (ILP)

Degree to which instructions can be overlapped or executed in parallel.

SIMD (Single Instruction, Multiple Data)

Parallel architecture where one instruction operates on multiple data elements simultaneously.

NUMA (Non-Uniform Memory Access)

Multiprocessor memory architecture giving each processor its own local memory with faster access than remote memory.

Direct-Mapped Cache

Cache mapping technique assigning each main-memory block to exactly one cache line.

Cylinder (Magnetic Disk)

All tracks on different platters located under the same read/write head position.

Sector

Smallest accessible storage unit on a magnetic disk, typically 512 bytes.

Hamming Code

Error-correcting code that adds parity bits to detect and correct single-bit errors.

NOR Flash

Flash memory with cells connected in parallel, allowing random byte access; slower writes, faster reads.

NAND Flash

Flash memory with cells connected in series, optimized for high-density, block-oriented access.

Cache Level L1

Smallest, fastest cache integrated directly into the processor core.

Memory Management Unit (MMU)

Hardware that translates virtual addresses to physical addresses.

Write-Through Cache

Write policy that updates both cache and main memory simultaneously on every write.

Write-Back Cache

Policy that updates main memory only when a modified cache line is evicted.

Multithreading

Technique that allows a processor to issue instructions from multiple threads to hide latency and improve utilization.

Amdahl’s Law

Formula estimating maximum speedup of a system when only part of it is improved or parallelized.

Instruction Cycle

Sequence of fetch, decode, execute, and write-back (sometimes indirect or interrupt) steps for each instruction.

Direct Memory Access (DMA)

I/O technique where a controller transfers data between memory and device without continuous CPU involvement, using cycle stealing.

Access Time

Time interval between a memory request and the completion of data delivery.

Latency

Delay before data transfer starts after an access request (seek + rotational delay on disks).

Superpipelined Processor

CPU design that divides instruction processing into more, finer pipeline stages to increase clock rate.

Thrashing

Condition where excessive paging or swapping keeps CPU busy with memory management rather than instruction execution.

Register Windows

Technique (e.g., SPARC) providing multiple overlapping register sets to reduce procedure call overhead.

Superscalar Processor

Architecture capable of issuing multiple instructions per clock cycle to parallel functional units.

RAID (Level 3)

Disk array with byte-level striping and a dedicated parity disk, providing fault tolerance.

RAID (Level 5)

Disk array with block-level striping and distributed parity, allowing one-disk fault tolerance with good read performance.

Solid-State Drive (SSD)

Mass-storage device using non-volatile flash memory; offers lower access times and higher reliability than HDDs.

De Morgan’s Theorem

Logic rule: NOT (A + B) = (NOT A) · (NOT B); NOT (A · B) = (NOT A) + (NOT B).

Interrupt Vector

Table or memory area containing starting addresses of interrupt service routines.

Operand Fetch

Phase of instruction execution that retrieves required operands from registers or memory.

DMA Cycle Stealing

Method where DMA controller temporarily borrows the bus, halting CPU memory access for one cycle to transfer data.

Superposition (ILP Hazard – Data)

Pipeline hazard arising when instructions require the same operand, causing read-after-write conflicts.

Hit Ratio (Cache)

Fraction of memory accesses satisfied by the cache without going to main memory.

Blu-ray Disc

High-definition optical disc capable of storing 25 GB per single-layer side.

Constant Angular Velocity (CAV)

Disk-spinning scheme maintaining fixed RPM so outer tracks pass under heads faster than inner tracks.

Write Instruction (I/O)

Command directing an I/O module to take data from the bus and send it to a peripheral.

Condition Codes (Flags)

Bits set by CPU hardware to record outcomes of arithmetic/logic operations (zero, carry, sign, overflow).

Orthogonality (ISA)

Design principle where instruction field choices (opcodes, addressing modes, registers) are independent, simplifying coding.

Opcode

Portion of an instruction that specifies the operation to be performed.

Stack Pointer (SP)

Register containing the address of the top element of the current stack.

Dynamic Random-Access Memory (DRAM)

Volatile memory technology requiring periodic refresh cycles.

Static Random-Access Memory (SRAM)

Fast volatile memory that uses bistable latching circuitry and does not need refreshing; used for caches.

Byte-Addressable Memory

Memory scheme where each byte has its own address; common in modern computers.

Flynn’s Taxonomy

Classification of parallel computer architectures into SISD, SIMD, MISD, and MIMD.

Instruction Set Architecture (ISA)

Formal specification of machine language instructions and programmer-visible registers for a processor family.