OCR A Level Computer Science - Structure and Function of the Processor

Key vocabulary flashcards covering CPU components, registers, buses, execution cycles, performance factors, and computer architectures from OCR Computer Science section 1.1.1.

Arithmetic and Logic Unit (ALU)

The component of the CPU that carries out all arithmetical and logical operations.

Control Unit (CU)

A component of the processor that directs the operations of the CPU, managing data flow, accepting and decoding instructions, and storing results back in memory.

Registers

Small memory cells operating at very high speeds used to temporarily store data where all arithmetic, logical, and shift operations occur.

Program Counter (PC)

A register that holds the address of the next instruction to be executed.

Accumulator (ACC)

A register that stores the results from calculations.

Memory Address Register (MAR)

A register that holds the address of a location that is to be read from or written to.

Memory Data Register (MDR)

A register that temporarily stores data that has been read or data that needs to be written.

Current Instruction Register (CIR)

A register that holds the current instruction being executed, divided up into operand and opcode.

Buses

A set of parallel wires connecting two or more components inside the CPU.

System Bus

The collective term for the data bus, address bus, and control bus in the CPU.

Bus Width

The number of parallel wires a bus has, which is directly proportional to the number of bits that can be transferred simultaneously.

Data Bus

A bi-directional bus used for transporting data and instructions between components.

Address Bus

A bus used to transmit memory addresses specifying where data is to be sent to or retrieved from.

Control Bus

A bi-directional bus used to transmit control signals between internal and external components.

Bus Request

A control signal showing that a device is requesting the use of the data bus.

Bus Grant

A control signal showing that the CPU has granted access to the data bus.

Memory Write

A control signal indicating that data is written into the addressed location using the bus.

Memory Read

A control signal indicating that data is read from a specific location to be placed onto the data bus.

Interrupt Request

A control signal showing that a device is requesting access to the CPU.

Clock Signal

A control signal used to synchronise operations across the processor.

Assembly Language

A low-level programming language that uses mnemonics to represent instructions, providing a simplified way of representing machine code.

Operand

The part of an instruction containing the data or the address of the data upon which the operation is to be performed.

Opcode

The part of an instruction specifying the type of instruction to be executed.

Pipelining

The process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer in close proximity to the CPU until required.

Fetch-Decode-Execute Cycle

The sequence of operations completed in order to execute an instruction.

Clock Speed

The time taken for one clock cycle to complete, determined by the system clock.

Core

An independent processor capable of running its own fetch-execute cycle.

Cache Memory

The CPU's onboard memory where instructions fetched from main memory are copied for quicker access if required again.

Von Neumann Architecture

A computer architecture built on the stored program concept using a single control unit, ALU, registers, and memory units with shared memory and shared data buses for data and instructions.

Harvard Architecture

A computer architecture with physically separate memories for instructions and data, commonly used in embedded processors.

Contemporary Processor Architecture

A architecture combining Von Neumann (for main memory) and Harvard architectures (dividing cache into instruction cache and data cache).