Pipelining
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65 Terms
What is pipelining in computer architecture?
An implementation technique where multiple instructions are overlapped during execution to improve throughput.
What is the main goal of pipelining?
To increase instruction throughput (instructions completed per unit time).
Does pipelining reduce the execution time of a single instruction?
No. Individual instruction latency remains roughly the same.
What performance metric does pipelining improve?
Program throughput.
What does CPI stand for?
Cycles Per Instruction.
What is the ideal CPI in a pipelined RISC processor?
Ideally, CPI = 1.
What is Instruction-Level Parallelism (ILP)?
The ability to execute parts of multiple instructions simultaneously.
What are the two major requirements for pipelining?
- Sufficient hardware resources 2. Independence between instructions
Why can dependencies hurt pipelining?
Because dependent instructions may need results that are not yet available.
What happens if data required by an instruction is not ready?
The pipeline stalls or uses forwarding/bypassing mechanisms.
What is a single-cycle processor?
A processor where each instruction completes in one long clock cycle.
What is a multi-cycle processor?
A processor where instructions are broken into stages executed across multiple cycles.
Why are multi-cycle processors more efficient than single-cycle processors?
They avoid wasted time by dividing instructions into smaller operations.
Name the classic 5 pipeline stages.
- IF – Instruction Fetch 2. ID – Instruction Decode 3. EX – Execute 4. MEM – Memory Access 5. WB – Write Back
What happens during the Instruction Fetch (IF) stage?
The processor fetches the instruction from memory.
What happens during the Instruction Decode (ID) stage?
The instruction fields are interpreted and operands are identified.
What happens during the Execute (EX) stage?
ALU operations are performed.
What happens during the Memory (MEM) stage?
Memory is accessed if required.
What happens during the Write Back (WB) stage?
Results are written back to registers and/or memory.
Why can multiple instructions overlap in a pipeline?
Because different hardware units handle different stages simultaneously.
When does the fetch unit become free?
After completing the fetch stage of an instruction.
Why can the next instruction begin fetching while the previous instruction decodes?
Because separate hardware resources are used.
What is pipeline fill time?
The time required before the pipeline starts producing completed instructions every cycle.
What is pipeline drain time?
The time needed to finish remaining instructions after no new instructions enter the pipeline.
After the pipeline is filled, how many instructions ideally complete per cycle?
One instruction per cycle.
Why does RISC use fixed-size instructions?
To simplify decoding and pipeline design.
What is the common instruction size in classic RISC?
32 bits.
Why is fixed instruction size beneficial?
The processor always knows where opcode and operands are located.
What information is stored in an instruction?
Opcode, source operands, destination operand, and function bits.
Why are registers important in RISC?
Most operations are performed directly on registers.
What does the Program Counter (PC) store?
The address of the next instruction.
Why does the PC typically increment by 4 bytes?
Because instructions are 32 bits (4 bytes) long.
What causes the PC to jump to another address?
Branch or jump instructions.
Why do branch instructions create problems in pipelines?
The processor does not immediately know which instruction comes next.
What is a pipeline hazard?
A condition that prevents the next instruction from executing during its designated cycle.
What are the three major types of pipeline hazards?
- Structural hazards 2. Data hazards 3. Control hazards
What causes a structural hazard?
Resource conflicts between instructions.
Give an example of a structural hazard.
Two instructions needing the same register or hardware unit simultaneously.
What causes a data hazard?
Dependencies between instructions.
What is a producer instruction?
An instruction that generates a value.
What is a consumer instruction?
An instruction that uses a value produced by another instruction.
Why does a consumer instruction sometimes stall?
Because the producer has not finished generating the needed data.
What could happen if the pipeline ignores a data hazard?
Incorrect computation due to garbage/old values.
Which pipeline stage detects operand dependencies?
Instruction Decode (ID).
What causes a control hazard?
Branch and jump instructions.
Why must the processor wait during a branch?
Because it must determine the correct next instruction address.
Which stage usually identifies a branch instruction?
Instruction Decode stage.
Why can excessive branching reduce performance?
Frequent branch resolution causes pipeline stalls.
What limits pipeline speed?
The slowest pipeline stage.
Why doesn’t deeper pipelining always improve performance?
Hazards and stalls reduce ideal gains.
What is the formula for average instruction execution time?
Execution Time = Clock Cycle Time × CPI
In an ideal pipeline, what determines execution time?
Mainly the clock cycle time.
Why might pipelining increase clock cycle time slightly?
Additional pipeline hardware and synchronization overhead.
If instruction 2 uses a value produced by instruction 1, what dependency exists?
A data dependency.
When is it safe for a dependent instruction to proceed?
When the required value has been produced.
Can an instruction still be fetched before dependency resolution?
Yes, because fetch does not yet require operand values.
Which stage actually requires operand values?
Decode stage.
What is a register physically implemented with?
Latches/flip-flops built from logic gates and transistors.
What is special about pipeline registers?
They are optimized for rapid read/write operations within cycles.
Why are pipeline registers important?
They hold intermediate results between stages.
Does pipelining change program execution order?
No, it preserves sequential correctness.
Why is maintaining execution order important?
To preserve correct program behavior.
What is the safest response to unresolved dependencies?
Stall the pipeline.
What does retired instruction mean?
An instruction that has completed execution successfully.
What is the biggest advantage of RISC for pipelining?
Simple, fixed-format instructions make pipeline stages easier and faster to design.