CPS590 Midterm -CH 1 & 2

os

operating system - uses CPU hardware to provide services to user

-manages secondary memory and I/O

processor

controls operation of computer (data processing)

CPU

name of one processor

main memory

stores data and programs, computer is volatile (loses info), disk is not. aka real or primary memory

I/O modules

external environment and devices

system bus

communicates between I/O modules, processors, main memory

MAR

memory address register - specifies memory address the address in memory for the next read or write

MBR

memory buffer register - contains data to be written into or read from memory

I/OAR

address register that specifies a particular I/O device

I/OBR

buffer register to exchange data between I/O module and processor

GPU

Graphical Processing Unit

SIMD

Single Instruction Multiple Data - techniques in super computers for handling data arrays

DSP

digital signal processors, streams audio and video streams

SoC

System on Chip - CPU, cache, GPU, DSP etc (other components, microprocessor only has CPU and cache)

fetch and execute cycle

basic instruction cycle -

1. PC increases as instruction is fetched

2. Processor reads + gets necessary data

3. Execute

instruction cycle actions

-Processor-Memory

-Processor-I/O

-Data processing (arith/logic)

-Control (alters execution seq)

opcode

first four bits in instruction (12 rest is address)

Interrupts

Classes:

Program

Timer

I/O

Hardware failure

Interrupts

improve processor utilization, stopping normal sequence of instructions to do task

Interrupts

Sections:

-instruction sequence - prepare for I/O op (eg copying data)

-I/O command

-sequence of instructions to complete operation

interrupt request

sent when I/O operation is ready to be serviced, processor suspends program and passes control to an interrupt handler to deal with

interrupt handler routine

An operating system routine that is called when an interrupt signal is received. Decides whether to handle based on priority (or disabled interrupts)

interrupt processing

1. The device issues an interrupt signal to the processor.

2. The processor finishes execution of the current instruction before responding

to the interrupt

3. The processor checks for interrupt request, if it finds one, sends acknowledgment signal to the device that issued the interrupt. The

acknowledgment allows the device to remove its interrupt signal.

4. The processor prepares to transfer control to the interrupt routine. (saves PC, PSW and address to control stack)

5. load interrupt handling address to PC

6. Saves processor register contents

7. Process interrupts

8. Ended process and get saved register values

9. Restore PSW and PC

PSW

program status word - minimum information required to save a program status

multiple interrupts

2 approaches:

-disable interrupts until new request signal

-handle based on priority

Memory Tradeoff

faster access time (speed)

greater capacity

cost

memory hierarchy

descending:

inc capacity

slower access time

cheaper

accessed less often

hit ratio

(H)T1 + (1-H)(T1 + T2)

average access time to two level memory

locality of reference

-memory locations recently referenced, and those near them, are likely to be referenced in the near future

-data tend to cluster

cache memory

A type of memory used to temporarily store frequently used data or programs for quick access; similar to RAM but faster.

cache design

Key elements of cache design:

1) Cache Size

2) Block Size

3) Mapping function

4) Replacement algorithm

5) Write policy

6 Number of cache levels

block size

larger size can increase hit ratio, but too big can decrease as blocks have to be moved out to make room for new ones

mapping function

determines where in cache blocks should be

replacement algorithm

chooses which block to replace when loading a new block (Least Recently Used)

write policy

dictates when to write to memory

eg. when block updated or block replaced (main memory obsolete)

DMA

Direct Memory Access - A technique for transferring data from main memory to a device without passing it through the CPU.

DMA can be performed on separate module on system bus or put in I/O module

I/O operations

3 techniques:

-programmed I/O

-interrupt-driven I/O

-Direct Memory Access

programmed I/O

I/O module performs action, sets bits in I/O status register, but no further action (no interrupt to processor, processor must actively read) - long wait/low performance

interrupt-driven I/O

I/O module interrupts processor when ready to exchange

-more efficient but has limited transfer rate due to processor test and service device

-processor is tied up and must execute a number of instructions for I/O module

DMA

-when processor wishes to read/write a block of data, issues command to DMA with info:

-whether R/W requested

-addr of I/O device involved

-starting location in memory to read/write data to

-number of words to be read or written

-I/O ops delegated to DMA, DMA interrupts when done

-DMA needs control of system bus = waiting for bus cycle

SMP

symmetric multiprocessors - multiple processors of similar power, who share memory and I/O, connected with a bus, can perform same functions, and controlled by an integrated os that helps processors interact with programs.

SMP advantages

Performance

Availability

Incremental Growth (add processors)

Scaling (variability of price and performance)