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von neumann architecture: basic concept
both the data and the software that are currently being used are stored in the computer memory (RAM) and a shared memory and bus are used for both instructions and data - in line w/ stored program concept
von neuman architecture: stored program concept
the machine code instructions are fetched from memory, decoded and executed in the processor​
von neuman architecture: components
control unit, ALU, buses and registers
von neumann architecture: why its useful
makes it easier to change tasks instead of rewiring by loading a different program into the memory
von neuman architecture: issues (4)
1. shared memory
2. memory leaks
3. data bus speed
4. data and instructions fetch rate
von neuman architecture: issues - data and instructions fetch rate
the rate at which data needs to be fetched is very different from the rate at which instructions are fetched, yet they still share the same data bus
von neuman architecture: issues - shared memory
both data and programs share the same memory, its possible for a defective program to over write another program in memory which could crash the system
von neuman architecture: issues - data bus speed
CPU runs much faster than the transfer speed of the data bus which leads to CPU spending much of its time waiting for data and instructions to arrive - von neumann bottleneck
von neuman architecture: issues - memory leaks
failure to release the memory which can cause insufficient memory for other programs to store
exam q: within a von neumann machine .............. are linked by a system bus
a processor, main memory and I/O controllers
harvard architecture: basic concept
has separate memories for instructions and data
harvard architecture: full explanation
memory is split into two parts, one for data and the other for program instructions
each part is accessed with a different bus, this allows CPU to fetch both data and instructions at the same time
harvard architecture: uses
used extensively with embedded Digital Signal processing (DSP) systems
harvard architecture: dsp applications - examples
audio, speech signal, biometrics, digital image, seismic, sonar and radar signal processing
harvard architecture: different memories can have different characteristics meaning....
- instructions may be read only while data may be read-write
- there could be more instruction memory than data memory, so larger word size is used for instructions
- instruction address bus may be wider than data bus
harvard architecture: why is it useful
- cpu can fetch data + instructions at same time, solving von neumann bottleneck
- faster than von neumann because data and instructions can be fetched in parallel
contemporary architecture: definition
modern high performance CPU chips uses both von neumann and harvard architecture
contemporary architecture: example
a main memory for holding both data and instructions but within the CPU cache memory, it is divided into an instruction cache and a data cache​
harvard vs von neumann: memory
separate data and instruction memory​ - memory units can have different characteristics (ROM/RAM)
harvard vs von neumann: memory
RAM used for data and instructions​
single control unit that sequentially works through instructions held in memory
harvard vs von neumann: address size
can be different for data and instructions adapted to needs
harvard vs von neumann: address size
same address size
harvard vs von neumann: number of buses
2 - one for instructions , one for data
harvard vs von neumann: number of buses
1 - shared
harvard vs von neumann: data/instructions
separate
harvard vs von neumann: data/instructions
together in same memory
harvard vs von neumann: programs
highly optimised - RISC
harvard vs von neumann: programs
instructions complex - CISC
harvard vs von neumann: uses
embedded systems and digital signal processors to do specific tasks
harvard vs von neumann: uses
conventional processors -PCs, servers, ​general-purpose computers to meet varying needs of end users
registers: why are they needed
faster access to most frequently used instructions and faster than accessing RAM