Sequential Logic Circuits

Sequential Circuit

A circuit whose output depends on a combination of inputs AND previous sequence inputs

State

Stored Bits

SR Latch

sequential circuit that is used to store memory

• 2 NOR Gates: Top has Set (s); bottom has Reset (r); output of either is the 2nd Input of the other

S R Output
0 0 Previous Output
1 0 Q = 1
0 1 Q = 0
1 1 RACE CONDITION (???)

Problem with SR Latch

If S and R are simultaneously high, the SR latch gets into a RACE condition, which provide a random output.

Best form of SR Latch

Level-Sensitive SR Latch

• 3 Inputs: Clock, Call, and Cancel Signal

Clock = 0 → Output = Previous Output (or dead 0 state)

Clock = 1:

• Call = 0 + Cancel = 1 → S=0, R=1 → Output = 0

• Call = 1 → S=1, R=0 → Output = 1

Avoiding RACE conditions requires technical build

Level Sensitive VS Edge Sensitive

All Talk About Clock

Level: Output changes when clk is in a certain state (high/low)

Edge: Output changes when clk changes b/w states (rising/falling)

D Latch

SR Latch where S = R’ with a clock signal
- ensures no RACE condition but WILL over multiple latches

Clk = 0 → Output = Previous Output (dead 0 state)

Clk = 1 → Output = SR Latch Logic w/ IDC of 00,11

Flip Flop

Bit Storage that stores states on the clk edge

Latch

Bit Storage that stores states on the clock state

D Flip-Flop

Changes state on the clock edge

• can be rising or falling edge

When clk 0→1:

D = 1 → Output = 1, D = 0 → Output = 0

When clk anything else:

Output = previous output

D Flip-Flop: Master-Servant

Characterized by Triangle on Bottom Left

2 Parts: Master and Servant D-latch. Only one enabled at a time

• clk = 0: from inverted clk, master enabled, loading D

• clk = 1: servant enabled, loading output from master

Value D when clk changes from 0→1 causes info change

Uses more transistors than Latches

Clock Signal

Oscillators create a pulsing signal

Period: Time for Full Cycle

Frequency: Amount of cycles in 1 second

Clock Cycle

Duration of 1 Period for a Clock Signal

D Flip-Flop: Master-Servant LOGIC

Cm = C’

Qm = Cm(rising)*Dm = Ds

Cs = C

Qs = Cs(rising)*Ds

Basic Register

multiple flip flops sharing a clock cycle

each flip flop has a unique inputs

allows storage of multiple bits

EXAMPLE: Temperature Display of Current and 2 Past Values

All Regs Bound on 1 Clock for every hour, changing temp display

Reg 1: Takes reading from Temp. Sensors and Outputs to Display

Reg 2: Takes Reg 1 Outputs and Uses as Inputs and Outputs

Reg 3: Takes Reg 2 Outputs and Uses as Inputs and Outputs

How do you capture a sequential circuits particular behavior over time with varying inputs?

FSM: Finite State Machine

Set of states representing every possible “mode” or “situation”

Arrows = clock cycle, Names on circles = states

Bool. on Arrows = Input needed for change

Bool. on Circles = Output of that state

State Diagram

Graphical Representation of Sequential Circuits

Akin to Equational Representation of Combinational Circuits

How to design sequential circuit?

1. Capture the Behavior of Function

   1. FSM → Controller Design/Architecture

2. Create Equations and Implement Gate-Based Circuit

   1. Encode States → Truth Table → SOP → Gates

EXAMPLE: Secure Car Key FSM

Wait: Starting State → Waits for Car CPU to request ID (a)

• a’ = loop back to wait a = advance to ID reading

Read 1-4 : Car Key transmits ID bit by bit each cycle

How to Capture Desired Behavior with an FSM?

1. List all Possible states w/ meaningful names

2. Create Transitions defined with all possible conditions

3. Refine the FSM with any improvements

How to Turn an FSM into a Controller?

1. Set Up Architecture

2. Encode States

3. Fill In the Truth Table

4. Implement & Simplify Combinational Logic