Embedded Systems 1 - Arm Assembly

ARM CPU - registers

30 registers, general purpose 32-bit, but only 15 visivle at a time

Register types

general: R0 to R12

SP or stack pointer, used by compilers for stack location: R14

PC register - points to next instruction, loaded with branch destination: R15

RISC attributes

instructions take one clock to execute, more advanced instructions such as multiplies, divides and FP instructions take more time

Load-Store Architecture

memory locations operations can only be move (load/store), load memory to registers/store memory from registers

What is a major difference between ARM RISC and x86 CISC?

all ALU instructions are done in ARM registers, which greately simplifiers the archiecture of the ARM processor

Four data types in ARM

Bit, Byte (8-bit), Half-word (two byte, 16-bit), word (4 byte, 32-bit)

MOV instruction

MOV R5, #5 --> can only be used when number can be represented in 12 bits

MOV R5, R2 (R5=R2)

MOV R0, XZR (XZR is a special register that always reads 0)

LDR instruction

LDR Rd, = k

- Rd = k //k is 32 bit

LDR X2, [X3] --> loads value at that address into X2 (creates a pointer)

LDR X0, =label --> loads address of a label

Simple Arithmetic Instructions

ADD R5, R2, R1 // R5 = R2 + R1

SUB R5, R9, #23 // R5 = R9 - 23 (immediate limited to 8 bits for ALU instructions)

Von Neumann Architecture

A processor where data and instructions are stored in the same memory and accessed via buses (same path), simpler but slower performance in high-power computing

Harvard Architecture

seperate memory for data and instructions, allows both data and instruction to be fetched simultaneously (parallel), but more complex

Modern Processors: Hybrid

VN for: main memory & I/O, less I/O

Harvard: internal cache with seperate instruction and data access, higher performance without bus contention

L1 Cache (RP4)

Harvard (smaller, seperate for instructions and data), faster access speed

L2 & main memory (RP4)

Von-neumann (1 MB shared by all), larger & more flexible

Memory Management Unit (MMU)

converts virtual addresses from programs to physical addresses for RAM

STR instruction (indirect addressing)

STR Rx, [Rd]

store contents of Rx into memory address in RD, square brackets means indirect addressing

LDR (Immediate addressing)

LDR Rx, =k

load constant value directly into register

LDR v. STR

LDR does memory address --> register, STR does register --> memory address

LDR R0, [R1] --> load value at R1 into register R0

STR R0, [R1] --> store value in R0 into memory address stored in R1

ARM is little endian

it means the LSB is stored at the lowest memory address

N-flag

Bit 31, N = 1 set is signed value is negative

Z-flag

Bit 30, Z = 1 set if result is 0

C-flag

Bit 29, C = 0 when there is a borrow (subtraction) and C = 1 if overflow with addition

V-flag

Bit 28, set (V=1) if there is signed overflow --> basically when a + num looks - or a - num looks +

real instructions

direct instructions to cpu such as mov and add

pseudo instructions

translated to real instructions by assembler such as ldr (allow for using intermediate loads of 32-bits while mov onyl allows for 8-bit)

assembler directives

ex) .data, .global (for the assembler, not translated to machine code) --> initialize variables, reserve memory, define sections (labels)

assembler directive: .text

tells assembler code section begins

assembler directive: .data

initialized data section begins

assembler directive: .global

inform assembler that a name or symbol will ne referenced in other files

assembler directive: .equ

sets values to variable names

assembler directive: .include

informs assembler to include information from another file

assembler directive: .extern

informs assembler code accesses a name defined in another file

RISC architecture

fixed instruction size, makes decoding easier, reduced number of transitors, load/store, hybrid architecture (VN & H), 32 registers, most instructions that take more than 1 clock --> but can lead to using more memory, inflexible

CISC Architecture

instructions have different lengths