C952 Assessment Glossary 20 PAGES

Vocabulary flashcards covering key terms from the C952 lecture notes on Computer Organization and Design.

wafer

A slice from a silicon ingot no more than 0.1 inches thick, used to make chips (dies).

state (sequential) element

a memory element such as register and memory.

• depends on both current inputs and and past history states.

Store (remembers the past data until it is changed); clocked input is present.

think of playing a video game and the game is saved at a checkpoint; it’s based on previous data saved.

updates on rising clock edge

combinational element

an operational element, such as AND gate or an ALU.

• AND, OR, NOT gates, adders, multiplexers, decoders.

calculate (no memory, pure logic)

depends ONLY on the output values.

a vending machine that gives you a option based on the button you pushed in that moment.

Normal instructional memory is modeled after this operational element.

die (or chips)

Individual rectangular sections cut from a wafer.

magnetic disk (HD)

It is an example of secondary memory with rotating platters coated with magnetic material.

-it is cheap, large, slow, and nonvolatile

LCD (flat display panel)

Liquid crystal display;

uses a thin layer of liquid polymers to transmit/block light when charged.

LAN

Local Area Network; network data within a campus or building.

WAN

Wide Area Network; network over a large geographic area.

abstraction

A model that hides lower-level details to simplify design of computer systems.

assemblers

A program that translates symbolic versions of instructions (e.g., ADD X3, X2, X1) into the binary version.

-the assembly language e.g., ARM, MIPS, etc.

operating system

Program that manages computer resources for programs running on the computer.

machine language

Binary representation used for communication within a computer.

CPU (processor)

Central Processing Unit; composed of the datapath and control unit.

datapath

Component of the processor that performs arithmetic and logic operations.

datapath elements

Functional units used to operate on or hold data within the processor.

ALU

Arithmetic Logic Unit; performs arithmetic and bitwise operations on integers.

A component part of the datapath on the CPU.

adders

Digital circuits that perform addition; used in the ALU and for calculating addresses, etc.

Theses are often used in the ALU, but also used in other parts of the processor where they table indices, increment counters, etc. 

register file

An array of processor registers in the CPU.

Modern computers usually use fast (static ram) SRAM.

multiplexer (mux, data selector)

A device that selects between several input signals and forwards the chosen input to one output.

This is similar to a control switch.

control

CPU component that commands the datapath, memory and I/O according to instructions of a program.

Compiler, Assembler, Linker, Loader

A high-level language program which is first compiled into an assembly language program and then assembled into an object module turned into machine language by the assembler.

The linker combines multiple assembly programs with library routines to resolve all references.

The loader then places the machine code into the proper memory locations for execution by the processor.

Think of Co-ALL…

cloud computing

a large collection of servers providing services over the Internet.

SaaS (Software as a Service)

Deliver software and data as a service over the Internet, usually via a browser that runs on local client devices.

e.g., web search engines like Google or social networking sites like Facebook.

transcompiler (or source-to-source compiler or transpiler)

A special type of compiler that converts a program's source code into another language.

It can also process a program written in an older version of a programming language, converting it to a newer version of the same language (this is not in the textbook).

binary digit (bit)

One of two base-2 digits: 0 or 1.

complier

A program that translates high-level language (e.g., Java, Python, etc.) into assembly language. 

register (or processor register)

A fast location for data on the CPU.

LEGv8

A subset of ARM instructions designed for the COD textbook.

a learning version that does not run on any real computer.

• Computer Organization and Design (COD) is the textbook.

LEGv8 operands

Registers and memory locations used in LEGv8 instructions

(e.g., ADD X1, X2, X3 uses X1, X2, X3).

register memory

2 ^ 62 memory words to store data structures, arrays, etc.

Addresses differ by 4, Memory[0], Memory[4], etc.

And 8 for double words, Memory[0], Memory[8], etc.

instruction set architecture (ISA)

Abstract interface between hardware and software.

Ex: ARM, LEGv8, MIPS, RISC, etc.

RISC — Reduced Instruction Set Computer

• uses a small, highly optimized set of simple instructions to perform tasks.

MIPS — Millions of Instructions Per Second

instruction set

The vocabulary of commands understood by an ISA.

MAD (multiply-add)

A single floating-point instruction that performs a compound operation: multiplication followed by addition.

A command commonly used in GPU programmable cores to increase floating-point instruction throughput.

opcode

Field in an instruction that tells the computer the format and operation.

This is not needed for the assessment LEGV8 R-format.

formats (or type) 

In ARM and LEGv8, all instructions are the same length.

So distinct instruction formats are used to distinguish between different kinds of instructions.

R-type format

(‘R’ for register). Used when all operands are registers.

I-type format

(‘I’ for immediate). Used if one operand is a constant (immediate).

D-type format

D-type/format (‘D’ for data). Used by data transfer instructions (loads and stores).

J-type format

J-type/format (‘J’ for jump). Used for branching.

short for a thread of execution (thread)

Threads are a way for a program to divide

(or split) itself into two or more simultaneously (or pseudo-simultaneously) running tasks.

synchronization

When parallel execution requires cooperation (such as when results of one process require results from another), it is necessary to know when a task is finished so that it is safe to read.

In this case, the tasks need to synchronize to prevent a data race.

data race

This can happen when dependent tasks are not synchronized.

lock/unlock

Used create synchronization and prevent data races by “locking” data in a process.

Least Significant Bit (LSB)

the rightmost bit in a word, e.g., 

1000 0100 0000 1110

Most Significant Bit (MSB)

the leftmost bit in a word, e.g., 

1000 0100 0000 1110

word

The “natural” unit of access in a computer, usually 32 bits (the word’s width).

• similar to double precision 32 bits.

floating-point

Arithmetic representing numbers in which the binary point is not fixed.

double precision

A floating-point value represented in two (hence double) 32-bit words.

• similar to word - usually are 32 bits.

overflow

When a result is too large to fit in the available number of bits provided.

overflow (flag)

Pertains to the number exceeding the allowed bit number.

For signed numbers, the flag is set when the sign gets flipped due to inadequate space.

Two Examples Below:

1. Two positives sum to a signed negative. 

0100 + 0100 = 1000

(overflow flag is turned on)

2. Two signed negatives sum to positive.

   1000 + 1000 = 0000

(overflow flag is turned on)

carry (flag)

For unsigned numbers. The flag is set when adding or subtracting two numbers carries into or to borrow from the most significant bit.

If treating the values as positives, the lost information leads to incorrect results.

Two Examples:

1. Two positives sum to a smaller positive. 

   1111 + 0001 = 0000

(carry flag is turned on)

2. Subtracting two positives results in a larger positive.

   0000 - 0001 = 1111

(carry flag is turned on)

However, on the assessment, the test writer may or may not understand this distinction; see #4 on the course planning tool and #9 on the pre-assessment.

program counter (PC)

Register containing the address of the instruction being executed.

It keeps the “count” of the instruction; we add to it as instructions are processed. 

exceptions

Conditions that halt instruction execution.

(e.g., overflow, hardware error)

system call

Special instruction transferring control from user mode to dedicated location, this invokes the exception mechanism in the process.

exception process

The PC (program counter) from the exception is saved in the Exception Link Register (ELR), and the processor is placed in supervisor mode.

To return to user mode from the exception, the Exception Return (ERET) instruction is used, which resets to user mode and jumps to the address in ELR.

ELR (Exception Link Register)

64-bit register holding the address of the affected instructions.

ESR (Exception Syndrome Register)

Register recording the cause of the exception.

• 32 bits in LEGv8

Used to prioritize multiple exceptions.

clock cycle time

(clock tick, clock and cycle, clock period)

Time for a single CPU clock cycle.

smallest can do; smaller = faster

Clock Cycle Formula:

CPU time =

CPI * Instruction count * clock cycle

rate (data rate)

Performance measure of bytes per unit of time second, e.g., GB per second.

This is the inverse of clock cycle time; CPU time formulas use one or the other.

Larger = faster

CPU time = (CPI * Instruction count)/clock rate

CPI (cycles per instruction)

Average number of clock cycles per instruction for a program. smaller = faster

total instructions (nonpipe) / pipeline

CPU time (CPU execution time)

The actual time the CPU spends computing a program (set of instructions).

Smaller = faster

CPU Time Formulas:

CPU Time formulas

Where:

← total clock cycles

When comparing performance:

1- (old speed) / (new speed)

throughput

Amount of data/instructions processed in a given time; “How much gets through.“

more is better.

pipelining

A technique in which multiple instructions are are overlapped in execution, like an assembly line or bucket brigade. 

pipeline hazard (or hazard)

Situations that prevent the next instruction in the instruction stream from being executed during its designated clock cycle. It improves instruction throughput rather than individual instruction execution time or latency.

• Hazards reduce the performance from the ideal speedup gained by pipelining.

data hazard

When an instruction in the pipeline process cannot execute because needed data is not available, i.e., it is waiting on a slower process.

data forwarding (bypass)

Technique to resolve data hazards by routing data from one pipeline stage to another.

control hazard (branch hazard)

Hazard when instruction flow depends on a decision (e.g., branch).

This occurs when the need to make a decision based on results from another instruction, e.g., when conditional branching.

branch prediction

Predicting the outcome of conditional branches to reduce hazards.

This is a method used to reduce branch hazards by anticipate likely outcomes of conditional branching.

structural hazard

When hardware cannot support the combination of instructions in a cycle.

pipeline stall (bubble)

A stall initiated to resolve a hazard.

superscalar

Technique to execute more than one instruction per clock cycle by selecting multiple instructions.

dynamic pipeline scheduling

Hardware support to reorder instruction execution to avoid stalls.

Superscalar processors use this scheduling process to take advantage of predictions (see zyBooks 4.10 or COD, pg 352).

exception (interrupt)

An unscheduled event that disrupts the program execution; used to detect overflow.

absolute address

A variable’s actual address in memory.

address

Value used to locate a data element within memory.

address translation (mapping)

Mapping a virtual address to a physical address.

Amdahl’s law

A rule that limits the theoretical speedup of a fixed workload of a system whose resources are improved. It applies to strong scaling. Also, see weak scaling.

In parallel computing, this law is mainly used to predict the theoretical maximum speedup (performance improvement) for program processing using multiple processors.

buffer (data buffer)

A region of memory used to temporarily store data while it is being moved from one place to another.

think of data stuttering…

limit register

A register which contains a certain number of bytes in the memory allocation

virtual address

A software visible address that is translated to a physical address.

Example: manufacturers use a 48-bit virtual address (gives 256 terabytes) instead of an 64 bit virtual address.

physical address

An actual address in main memory.

48 bit - virtual address

Virtual address space using 48 bits for addressing.

CPU manufacturers use a 48-bit virtual address.

page table (map)

Table containing virtual-to-physical address translations in virtual memory.

page fault

An accessed page is not present in main memory.

page table register

Register holding the location of the page table for a process.

reference bit (or use bit or access bit)

A value that is set whenever a page is accessed.

It allows optimization methods to be implemented.

• e.g., replacing the least recently used block.

TLB (translation-lookaside buffer)

A cache that stores recently used address mappings. Similar to the “favorites” list on a phone’s contact list, a TLB takes advantage of the temporal and spatial locality to avoid the double memory accesses of getting the physical address and then the data. 

memory paging (paging)

A memory management scheme that uses fixed-size blocks (it’s what the book focuses). As opposed to (memory) segmentation which uses variable-size blocks. 

demand paging

Disk pages loaded into memory only when accessed (on a page fault).

demand paging A method of virtual memory management where the OS copies a disk page into memory only if an attempt to access a page that does not exist (i.e. a page fault occurs). That is, pages are created after they are demanded. As opposed to anticipatory paging (or swap prefetch) anticipates page references to minimize future page faults.

virtual machine (VM)

A software-emulated computer with its own VM state.

It is a state or a process given by a page table, program counter, registers using a virtual machine.

The virtual state must be saved if ANOTHER virtual machine is going to use the processor.

VM state

State or process of a VM defined by page table, program counter, and registers. The state must be saved if another VM is to be use the processor.

hypervisor / VMM (virtual machine montior)

Software that supports VMs and maps virtual resources to physical resources.

Hypervisor (or virtual machine monitor VMM) The software that supports VMs; the heart of VM technology. The VMM determines how to map virtual resources to physical resources.

memory hierarchy

Structure with multiple levels of memory; faster but smaller near the CPU, slower but larger farther away.

memory hierarchy a structure with multiple levels of memories; as you move away from the CPU, memory gets slower, larger, and cheaper. 

main memory (primary memory)

Volatile memory used during processing; typically DRAM.

main memory (or primary memory) Volatile memory used to hold programs (sets of instructions) while they are being processed; typically DRAM.

secondary memory

Non-volatile storage, e.g., magnetic disks or SSDs.

secondary memory Non-volatile memory used to store data between running programs; typically magnetic or SSD disks. 

ROM

Read-Only Memory; non-volatile

DIMM

Dual Inline Memory Module; DRAM-containing memory module.

DIMM Dual inline memory module. A small board that contains DRAM chips on both sides. SIMMS has DRAMs on only one side, They are both plugged into memory slots on a motherboard.

DRAM (Dynamic Random Access Memory)

DRAM Dynamic Random Access Memory. Memory built as an integrated circuit providing random access to any location. The electric charge on the capacitors slowly leaks off, so without intervention, the data on the chip would soon be lost.

To prevent this, DRAM requires an external memory refresh circuit that periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed.

Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

SIMM

Single Inline Memory Module; older memory module with DRAM on one side.