Routing, Interconnect, and Physical Delay

Routing

The process of selecting programmable wires, switch points, and connection resources that physically realize logical netlist connectivity between placed FPGA cells.

Logical Net

A logical communication relationship specifying that a source must connect to one or more destinations.

Physical Route

The particular path through FPGA interconnect that physically realizes a logical net after routing.

Logical Net → Physical Route

The implementation transition in which an abstract connectivity requirement becomes a specific physical path through FPGA interconnect.

Programmable Interconnect

The physical FPGA circuitry used to carry signals between placed resources.

Programmable Wire

A routing resource through which a signal can physically travel inside the FPGA.

Switch Point

A programmable routing element used to connect portions of FPGA interconnect.

Connection Resource

A physical routing resource used to establish communication between placed cells.

Source

The cell or output that drives a logical net.

Destination

The cell or input that receives the value carried by a routed net.

RTL Signal Name

Describes a logical relationship, not the exact physical path that the implemented signal will take through the FPGA.

Same RTL, Different Physical Routes

Different implementations of the same RTL may assign different physical paths to the same logical communication relationship.

Routing Is Part of the Machine

Programmable interconnect is physical circuitry whose properties contribute to implementation behavior.

Finite Connectivity

FPGA interconnect cannot connect everything arbitrarily; routing must use the connectivity physically provided by the device.

Interconnect Delay

Time introduced while a signal travels through the physical FPGA routing network.

Interconnect Capacitance

A physical property of routing circuitry that contributes to the cost of moving signals through the FPGA.

Interconnect Power Cost

Physical signal routing consumes power and therefore contributes to implementation cost.

Implemented Data Path

A physical path in which time is spent both inside computational resources and travelling through interconnect between them.

Logic Delay

Time spent propagating through computational resources such as LUT or arithmetic logic.

Routing Delay

Time spent propagating through the physical interconnect between computational resources.

Logic Delay vs Routing Delay

Logic delay comes from computation inside resources; routing delay comes from physical communication between resources.

Clock-to-Q

The launch delay from the active clock event until the launching flip-flop's output responds.

Launch Flip-Flop

The storage element from which a synchronous data path begins.

Capture Flip-Flop

The storage element at which a synchronous data path ends.

Launch FF → Logic → Route → Logic → Route → Capture FF

A physical view of a synchronous data path showing that both computation and communication contribute to the path.

Simple RTL Path

A logically simple path that can still become physically expensive if its implemented communication route is long or difficult.

Long Physical Route

Can increase routing delay even when the corresponding RTL relationship appears simple.

Well-Placed Structure

May benefit from shorter local connections and therefore reduced routing work.

Dedicated Arithmetic Connectivity

Specialized local FPGA connectivity that can help arithmetic structures communicate efficiently when the implementation maps appropriately.

Physical Origin of Routing Delay

Routing delay arises because signals must travel through real programmable wires, switches, and connection resources between placed cells.

Communication Cost

Physical implementation cost associated with transporting information between resources rather than performing the logical computation itself.

Physical Path Cost

Depends not only on the logic being computed but also on how the placed resources must communicate through FPGA interconnect.

Placement and Routing Are Coupled

Where cells are placed influences what physical routes are available and how expensive their communication may become.

Placement Answers

Where do the cells physically live?

Routing Answers

How do those physically placed cells communicate?

Synthesis vs Placement vs Routing

Synthesis determines the resource-level machine; Placement assigns cells to physical sites; Routing assigns logical nets to physical communication paths.