Difference Voltage Generator [Part III]

VCC & VEE

Power rails supplying +15 V (VCC) and –15 V (VEE) to the op-amps, enabling symmetrical signal swing around 0 V.

Voltage Divider (R4–R3–R5)

Resistors 6.8k–1k–6.8k create a midpoint bias. The middle node (VDM) receives an input ramp voltage defined by the simulation.

VDM Source

A piecewise linear (PWL) voltage source that ramps from –1 V to +1 V over 10 ms, serving as the test signal.

U1A (Buffer)

First op-amp in unity-gain configuration, copying the VDM input while lowering its output impedance for stable driving.

U1B (Differential Amplifier)

Second op-amp with matched resistors (R1 = R2 = 10k). Produces an inverted version of VDM, acting as a difference amplifier with gain = –1.

VREFN

The negative ramp output, inverted by U1B (+1 V to –1 V).

VREFP

The positive ramp output, directly taken from the buffered VDM signal (–1 V to +1 V).

Differential Pair (VREFP & VREFN)

Together they form a symmetrical differential voltage,
Vdiff = Vrefp - Vrefn = 2*VDM
This makes the ramp twice as large when measured differentially.

Generates clean differential reference signals for ADC testing, measurement systems, or any circuit requiring a balanced ramp input.

Application of this circuit