1.1 - Fetch-Execute Cycle
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Before cycle can take place...
Instructions translated into machine code
Program instructions loaded from secondary storage into RAM
Program instructions loaded from secondary storage into RAM
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When are interrupts checked for?
After each cycle
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Fetch
Address of next instruction: PC to MAR (+PC incremented)
Instruction at the address: RAM to MDR
MDR to CIR (so MDR is freed up for execute)
Instruction at the address: RAM to MDR
MDR to CIR (so MDR is freed up for execute)
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Decode
CIR instruction decoded
Split into operand and opcode. Additional data fetched if required
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Execute
The instruction is executed by ALU and the result is held in accumulator or stored in RAM
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Opcode vs operand
Opcode: Instruction
Operand: Data/data address to be manipulated
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Note 
Flashcards (42)