1.1 - Fetch-Execute Cycle

Before cycle can take place...

Instructions translated into machine code
Program instructions loaded from secondary storage into RAM

When are interrupts checked for?

After each cycle

Fetch

Address of next instruction: PC to MAR (+PC incremented)
Instruction at the address: RAM to MDR
MDR to CIR (so MDR is freed up for execute)

Decode

CIR instruction decoded
Split into operand and opcode. Additional data fetched if required

Execute

The instruction is executed by ALU and the result is held in accumulator or stored in RAM

Opcode vs operand

Opcode: Instruction
Operand: Data/data address to be manipulated