COMP2220 – СOMPUTER SYSTEMS ARCHITECTURE

If signed numbers are represented using 4 bits, what is the answer of 5₁₀ - 6₁₀, and will an overflow occur?

A) 0001 / overflow
B) 1011 / no overflow
C) 1001 / overflow
D) 1111 / no overflow

Correct Answer: B) 1011 / no overflow

QUESTION 3
Which selection of components below results from descending the memory hierarchy?

A) Cache, Magnetic Disk, Magnetic Tape, Registers
B) CD-ROM, Main Memory, Cache, Magnetic Tape
C) Cache, Main Memory, Magnetic Disk, Magnetic Tape
D) Cache, Registers, CD-ROM, Magnetic Tape

C) Cache, Main Memory, Magnetic Disk, Magnetic Tape

For the current instruction being executed the instruction register stores,

A) Instruction opcode
B) The result of the last data operation
C) Instruction operand
D) None of the above

Correct Answer: A) Instruction opcode

Given a single error correction (SEC) Hamming code system that employs eight-bit data words, if the 4-bit syndrome word is equivalent to 1111, then this means

A) No error correction is required
B) The detected error cannot be corrected
C) Error correction is required
D) None of the above

C) Error correction is required

To which of the following buses is main memory connected?

A) High-performance bus
B) Expansion Bus
C) Control bus
D) System Bus

D) System Bus

In an Interrupt-driven I/O, when an interrupt is detected, details on the current processor condition is stored in

A) Return address register
B) Program counter
C) Program status word
D) Memory bank

C) Program status word

Which element/technology is used in second generation computers?

A) Silicon Wafer
B) Transistors
C) Capacitance Emitter
D) Vacuum Tube

B) Transistors

The law that measures the processing speedup when using a parallel processor with N processors defined by the equation below is known as:

speedup=time to execute program on a single processortime to execute program on N parallel processors\text{speedup} = \frac{\text{time to execute program on a single processor}}{\text{time to execute program on N parallel processors}}speedup=time to execute program on N parallel processorstime to execute program on a single processor​

A) Amdhal’s Law
B) Murphy’s Law
C) Archimedes’ Principle
D) Moore’s Law

A) Amdahl's Law

Which of the following is not a memory access method?

A) Sequential Access
B) Synchronous Access
C) Direct Access
D) Random Access

B) Synchronous Access

Identify the addressing mode which provides the fastest access to the operand.

A) Register Addressing Mode
B) Immediate Addressing Mode
C) Direct Addressing Mode
D) Base-Register Addressing Mode

A) Register Addressing Mode

Which RAID level has the characteristic of mirroring the data from N independent disks such that 2N disks total are required?

A) RAID 0
B) RAID 2
C) RAID 1
D) RAID 5

C) RAID 1

Which of the following is not a class of interrupt?

A) Timer
B) Program
C) Hardware failure
D) User

D) User
[only gemini said program]

The systems bus is comprised of which three buses?

A) Data bus, Instruction bus, Address bus
B) Instruction bus, Control bus, Address bus
C) Control bus, Power bus, Expansion bus
D) Address bus, Control bus, Data bus

D) Address bus, Control bus, Data bus

From the following, which type of memory is not a read-mostly memory?

A) EEPROM
B) PROM
C) Flash
D) EPROM

A) EEPROM

What term describes the scanning of information at the same rate by rotating a disk at a fixed speed?

A) Constant angular velocity
B) Frequency
C) Rotational delay
D) Constant linear velocity

A) Constant angular velocity

10. Select the most appropriate simplification result for the Karnaugh Map below.

BC\A	00	01	11	10
0	0	X	1	X
1	1	1	1	1

A) B+AC
B) B+AC
C) AC+AB+BC
D) B+AC

D) B+AC+AC‾B + AC + A\overline{C}B+AC+AC

Which is the most efficient replacement algorithm assuming a direct mapping scheme?

A) Least Recently Used
B) Least Frequently Used
C) FIFO
D) None of the above

D) None of the above

If signed numbers are represented using 4 bits, what is the answer of −210−610-2_{10} - 6_{10}−210​−610​, and will an overflow occur?

A) 1111 / overflow
B) 1100 / no overflow
C) 1000 / overflow
D) 1000 / no overflow

D) 1000 / no overflow

Which of the following is not the function of an I/O Module?

A) Device Communication
B) Error Correction
C) Data Buffering
D) Vacuum Tube

D) Vacuum Tube

Which of the following combination of instruction cycle states involves data movement only?

A) Instruction Fetch, Data Operation, Operand Address Calculation
B) Instruction Address Calculation, Operand Store, Data Operation
C) Data Operation, Instruction Address Calculation, Operand Address Calculation
D) Instruction Fetch, Operand Fetch, Operand Store

D) Instruction Fetch, Operand Fetch, Operand Store

Which of the following best describes the constituent components of the systems bus?

A) Data bus, Instruction bus, Address bus, Control bus
B) Instruction bus, Control bus, Address bus
C) Control bus, Power bus, Expansion bus
D) Address bus, Control bus, Data bus

D) Address bus, Control bus, Data bus

What important value does the program counter register store?

A) Instruction opcode
B) Program instruction offset value
C) Address of the currently executing program instruction
D) None of the above

C) Address of the currently executing program instruction

Where are the details of the current processor condition stored when an interrupt is detected assuming an Interrupt-driven I/O?

A) Return address register
B) Program counter
C) Program status word
D) Memory bank

C) Program status word

Which redundant array of independent disks (RAID) level is based on replicating data across two or more disks?

A) RAID 0
B) RAID 2
C) RAID 1
D) RAID 3

C) RAID 1

Which selection of components below results from descending the memory hierarchy?

A) Cache, Magnetic Disk, Magnetic Tape, Registers
B) CD-ROM, Main Memory, Cache, Magnetic Tape
C) Cache, Main Memory, Magnetic Disk, Magnetic Tape
D) Cache, Registers, CD-ROM, Magnetic Tape

C) Cache, Main Memory, Magnetic Disk, Magnetic Tape

Multiple parallel pipelines are used in:

A) Speculative execution
B) Data flow analysis
C) Superscalar execution
D) Branch prediction

C) Superscalar execution

Which element/technology is used in third generation computers?

A) Microelectronics
B) Transistors
C) Capacitance Emitter
D) Vacuum Tube

A) Microelectronics

Which of the following components below results from descending the memory hierarchy?

Answer: Cache, Main Memory, Magnetic Disk, Magnetic Tape

Which of the following substrates for magnetic disks has better capacity to withstand shock and damage?

Options:

• Glass

• Resin

• Quartz

• Poly-crystalline

Answer: Glass

Which register temporarily stores the result of a processor calculation?

Options:

• Accumulator

• Program Counter

• Instruction Register

Answer: Accumulator

Which law states that the number of transistors on an integrated circuit doubles approximately every 18 months?

Options:

• Moore’s Law

• Murphy’s Law

• Amdahl’s Law

• Archimedes’ Principle

Moore’s Law

Select one correct statement:

Options:
a) Structure refers to the operational units and their interconnections that realize the architectural specification.
b) Function refers to the hierarchical relationship between the components within a computer system.
c) Computer organizational attributes include addressing techniques and hardware details that are transparent to the programmer.
d) I/O mechanisms and data sizes are attributes of computer architecture.

a) Structure refers to the operational units and their interconnections that realize the architectural specification.

if a 4-bit syndrome word is equivalent to 0000, what does this indicate in error detection/correction?

NO ERROR CORRECTION IS REQUIRED (the data is error-free).

In a certain computer, an instruction is composed of two fields: the opcode and an operand address. What is the minimum size of the opcode (in bits) if an instruction set of 300 opcodes is required?

Options:

• 7 bits

• 8 bits

• 9 bits

• 10 bits

Answer:

2n≥300  ⟹  n=⌈log⁡2(300)⌉=9 bits2n≥300⟹n=⌈log2​(300)⌉=9 bits

(9 bits are needed to represent 300 unique opcodes.)

To which bus is main memory connected?

Options:

• Control bus

• Expansion bus

• Instruction bus

• System bus

System bus

n which type of timing does the clock act as a reference?

Options:

• Asynchronous timing

• Interrupt timing

• Sequential timing

• Synchronous timing

✅ Answer: Synchronous timing

In an interrupt-driven I/O, when an interrupt is detected, details on the current processor condition is stored in:

Options:

• Return address register

• Program Counter (PC)

• Memory bank

• Program Status Word (PSW)

Program Status Word (PSW)

If signed numbers are represented using 4 bits, what is the answer of 710+(−4)107_{10} + (-4)_{10}710​+(−4)10​, and will an overflow occur?

Options:

• 1011 / no overflow

• 1001 / overflow

• 1100 / no overflow

• 0011 / overflow

0011 / overflow

Given that a hypothetical random access memory (RAM) has an access time and memory recovery time of 20 and 30 units respectively, what is the maximum transfer rate for this memory?

Options:

• 1 / (20 units)

• 1 / (30 units)

• 1 / (20 units + 30 units)

• 50 units

Maximum Transfer Rate=Access Time+Recovery Time1​=20+301​=501​ transfers per unit time.

Which element/technology is used in third generation computers?

Options:

• Vacuum Tube

• Transistors

• Microelectronics

• Silicon Wafer

Silicon Wafer

Clearly distinguish between the following terms:
Direct Memory Access (DMA) and Direct Access Method (DAM)

Options/Explanations:

• Direct Memory Access (DMA):

  • Allows peripherals to access memory directly without CPU intervention

  • Reduces CPU load and improves data transfer efficiency

  • Example: Hard drive transferring data to RAM without CPU usage

• Direct Access Method (DAM):

  • Refers to accessing data from storage (e.g., disks) without sequential access

  • Enables random access to specific data locations

  • Example: A database system accessing records non-sequentially

• DMA is about bypassing the CPU during data transfer

• DAM is about how data is retrieved from storage (non-sequentially)

• DRAM is cheaper, slower, and requires refreshing

• SRAM is faster, more expensive, and does not require refreshing

Clearly distinguish between the following terms:
DRAM and SRAM

Options/Comparison Table:

Feature	DRAM	SRAM
Storage Mechanism	Capacitors (needs refreshing)	Flip-flops (no refreshing)
Speed	Slower	Faster
Cost	Cheaper	More expensive
Density	Higher (more storage per chip)	Lower
Power Consumption	Lower when idle, higher when active	Generally higher overall
Applications	Used in RAM (main memory)	Used in cache (CPU)
Latency	Higher latency	Lower latency

Clearly distinguish between the following terms:
Computer Architecture and Computer Organization

Options/Comparison:

• Computer Architecture:

  • Defines the conceptual design and behavior of the system

  • Focuses on instruction sets, processor design, memory hierarchy, and I/O

  • Example: x86 or ARM architecture, which defines how the CPU functions

• Computer Organization:

  • Deals with the physical implementation of the architecture

  • Focuses on how components like registers, buses, and ALUs are structured to execute instructions

  • Example: Register layout, pipeline stages, and data flow within the CPU

• Architecture = What the system does (logical design)

• Organization = How the system does it (physical implementation)

QUESTION 2b
Consider a processor with access to two levels of memory.

• Level 1 (L1 cache): 16K words, 120 ns access time

• Level 2 (main memory): 256M words, 800 ns access time

• Hit ratio = 90%

• Neglect time to check L1

What is the average memory access time (AMAT)?

To calculate the Average Memory Access Time (AMAT) for a two-level memory hierarchy, we use the following formula:

AMAT=Hit Time+Miss Rate×Miss PenaltyAMAT=Hit Time+Miss Rate×Miss Penalty

Given:

• L1 Cache:

  • Access time (Hit Time) = 120 ns

  • Hit ratio = 90% (0.9)

  • Miss ratio = 1 - Hit ratio = 10% (0.1)

• Main Memory:

  • Access time (Miss Penalty) = 800 ns

• Time to check L1 is negligible (already included in L1 access time).

Calculation:

1. Hit Time (L1):
   When data is found in L1 (90% of the time), the access time is 120 ns.

2. Miss Penalty (Main Memory):
   When data is not in L1 (10% of the time), we must access main memory, taking 800 ns.

3. Average Memory Access Time (AMAT):

   AMAT=L1 Hit Time+(L1 Miss Rate×Main Memory Access Time)AMAT=L1 Hit Time+(L1 Miss Rate×Main Memory Access Time)AMAT=120 ns+(0.1×800 ns)=120 ns+80 ns=200 nsAMAT=120ns+(0.1×800ns)=120ns+80ns=200ns

Final Answer:
The average memory access time is 200 ns200ns​.


Another answer given was 188ns


AMAT = (Hit Ratio × L1 Access Time) + (Miss Ratio × L2 Access Time) AMAT = (0.90 × 120 ns) + (0.10 × 800 ns) AMAT = 108 ns + 80 ns AMAT = 188 ns