1.1.1. Structure and Function of the Processor: Characteristics of Contemporary Processors: Computer Science A-Level OCR

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35 Terms

1
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What does the Arithmetic and Logic unit

do?

The ALU completes all the arithmetical

and logical operations.

2
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What is the Control Unit?

A part of the processor which directs

operations inside the CPU.

3
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What are registers?

Small memory cells that operate at high

speeds.

4
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Where do all the arithmetic, logic, or shift

operations occur?

They occur in registers.

5
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What does the Program Counter (PC)

do?

The Program Counter holds the address

of the next instruction.

6
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In which part of the CPU do all

calculations take place?

The Arithmetic and Logic Unit (ALU).

7
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Where are intermediate arithmetic and

logic results stored?

In the accumulator (ACC).

8
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What does the Memory Address Register do?

Holds the address of a location that is to be read from or written to.

9
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What does the Memory Data Register

do?

Temporarily stores the data that has just

been read from or the data needs to be

written.

10
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What does the Current Instruction

Register do?

Holds the current instruction divided up

into opcode and operand.

11
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What is a Bus?

A set of parallel wires connecting two or more components together.

12
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What is the system bus?

The collection of the data bus, address bus, and control bus is called the system bus.

13
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What is the width of a bus?

The number of parallel wires it has.

14
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What is the data bus?

A bidirectional bus used to transport data and instructions between components.

15
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What is the control bus?

The bi-directional bus used to transmit control signals between internal and external components.

16
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What is the address bus used for?

Used to transmit the memory address specifying where data is to be sent from or retrieved from.

17
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What does adding a wire to the address

bus do to the number of addressable

locations?

It doubles the number of addressable locations.

18
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What does the Bus Request indicate?

indicates a device is requesting access to the data bus.

19
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What does Bus Grant indicate?

Indicates the CPU has granted access to the data bus.

20
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What does memory write do?

Causes the data on the data bus to be written into the addressed location

21
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What does memory read do?

Causes the data from the addressed location to be placed onto the data bus.

22
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What does the interrupt request control signal indicate?

Indicates that a device is requesting access to the CPU.

23
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What is the clock control signal used for?

It is used to synchronise instructions.

24
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What is Assembly Language?

Assembly Language is a programming language where mnemonics are used to represent instructions.

25
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What is opcode?

Opcode is used to determine the type of instruction and what hardware to use to execute it.

26
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What is the operand?

The operand is the address of where the operation is performed.

27
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What occurs during the fetch phase?

- The address from the PC is copied to the MAR,

- Instruction held at that address is copied to the

MDR by the data bus, simultaneously the

contents of the PC is increased by 1,

- The value of the MDR is copied to the CIR

28
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What occurs during the decode phase?

The contents of the CIR is split into operand and opcode.

29
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What occurs during the execute phase?

The opcode is executed on the data.

30
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What is the clock speed?

The number of clock cycles completed per second.

31
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What is cache memory?

Cache memory is the CPU’s onboard memory which can be accessed a lot faster than main memory

32
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What is pipelining?

The process of completing the fetch, decode and execute of three separate files simultaneously.

33
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What is Von Neumann architecture?

Architecture in which there is a single shared memory and shared data bus for both data and instructions.

34
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What is Harvard architecture?

Architecture in which there is two separate memory and data buses for data and instructions.

35
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What is contemporary processing?

Processing in which Von Neumann architecture is used for main memory. Cache uses Harvard architecture, divided into instruction cache and data cache