15.1 Processors & Parallel Processing

RISC

- reduced instruction set computer

CISC

- complex instruction set computer

Pipelining

- allows several instructions to be processed simultaneously

- without having to wait for previous instruction to finish

- increases number of instructions completed per unit time

- compatible with RISC

Parallel Processing

- operation that allows a process to be split up

- each part to be executed by different processor at the same time

SISD

- single instruction single data

- architecture that uses single processor & 1 data source

- parallel processing not allowed — single processor

- e.g early personal computers

SIMD

- single instruction multiple data

- architecture that uses many processors & many data sources

- each processors executes the same instruction but with diff data inputs

- array processor

- for e.g sound sampling

MISD

- multiple instructions single data

- architecture that uses multiple processors & 1 data source

- each processor executes diff instructions — uses shared data source

MIMD

- multiple instructions multiple data

- architecture that uses multiple processors & multiple data source

- each processor executes instructions independently, uses data from a separate source

- multi core system

Cluster

- no of processors networked together

CISC

- many instruction formats

- more addressing modes

- multi-cycle instructions

- variable length instructions

- longer execution time for instructions

- decoding instructions is complex

- design emphasis on hardware

RISC

- fewer instruction formats

- fewer addressing modes

- single clock-cycle instructions

- fixed length instructions

- faster execution time for instructions

- make use of general multi-purpose registers

- design emphasis on software

Stages of Pipelining

- IF (Instruction Fetch Cycle)

- ID (Instruction Decode Cycle)

- OF (Operand Fetch Cycle)

- IE (Instruction Execution Cycle)

- WB (Write Back Result Process)

Interrupt In Pipelining

- If Interrupt In Pipelining Received

1. Discard all instructions except for the one in WB Stage (so work can be saved)

2. Interrupt Handling Routine Applied

3. Once serviced, processor restarts with next instruction in sequence

Interrupt In Pipelining (Alternate)

- If Interrupt In Pipelining Received

1. Content of 5 stages stored in registers

2. Once interrupt is serviced, processor restores the previous status

3. Once serviced, processor restarts with next instruction in sequence

Massively Parallel Computer Systems

- multiple computer containing SIMD processors — networked together to form a cluster

- processor from each computer forms a part of larger pseudo parallel system

- by linking this way — processing power inc

- each processor will carry out processing & simultaneously process set of coordinated instructions

- communicate through interconnected data pathways

Virtual Machines

- emulation of existing computer system

- computer OS running within another computer's OS

Examples Of Roles Of Virtual Machines

- Guest OS

- Host OS

Guest OS

- OS running in VM

- controls virtual hardware during the emulation

- OS is emulated within host OS

- running under control of Host OS Software

Host OS

- OS controlling the actual physical hardware

- normal OS for the physical computer

- monitors the VM

- runs the VM

Benefits Of VM

- Guest OS can be used without impacting Host OS — if software emulating in Guest OS causes system crash, VM protects from other softwares in host os

- Test new OS or Apps or existing hardware, without purchasing additional hardware

- Emulate apps which are not compatible with Host OS

Limitations Of VM

- Likely Guest OS not same performance as original system

- quite expensive for a larger company

- complex to manage & mantain