Functions and Structures of a CPU:

CH1 of A-Level Computer Science

Program Counter (PC)

Program Counter (PC)

Holds the address of the next instruction to be executed.

Status Register

Holds the flags that indicate the outcome of various different operations.

Accumulator

Holds intermediate arithmetic and logic results from the ALU.

Current Instruction Register (CIR)

Holds the current instruction that is being executed.

Arithmetic Logic Unit (ALU)

Performs all logical and arithmetic operations. (these being addition, subtraction, AND, OR operations).

Control Unit (CU)

Directs the operations of the processor, it tells the ALU, memory and I/O devices how to respond to the instructions sent to the processor.

Memory Buffer/Data Register (MBR/MDR)

Temporarily holds data that is being transferred to or from the computers main memory.

Memory Address Register (MAR)

Holds the memory address of the data that needs to be accessed by the CPU.

General Purpose Registers

Used for temporary storage of data during execution.

Fetch (FDE Cycle)

The fetch step is the first phase of the Fetch-Decode-Execute (FDE) cycle in a computer's CPU. During this step:

1. Program Counter (PC): The CPU uses the Program Counter to determine the address of the next instruction to be executed.

2. Memory Access: The instruction at that address is fetched from memory (RAM).

3. Instruction Register (IR): The fetched instruction is then loaded into the Instruction Register for decoding.

This step is crucial for the CPU to know what operation to perform next.

Decode (FDE Cycle)

The decode step in the Fetch-Decode-Execute (FDE) cycle involves interpreting the instruction fetched from memory. Here’s how it works:

1. Instruction Register: The fetched instruction is stored in the instruction register.

2. Opcode Identification: The control unit identifies the opcode (operation code) which specifies the operation to be performed.

3. Operand Extraction: If the instruction requires operands, the necessary data is identified, which may involve accessing registers or memory.

4. Control Signals: The control unit generates signals to direct the necessary components of the CPU for the execution phase.

This step is crucial for determining what action the CPU will take next.

Execute (FDE Cycle)

The Execute step is the third phase in the Fetch-Decode-Execute (FDE) cycle of a CPU. During this phase:

1. Operation Execution: The CPU performs the operation specified by the decoded instruction. This may involve arithmetic or logical operations, data transfer, or control operations.

2. ALU Involvement: The Arithmetic Logic Unit (ALU) is often used to carry out calculations or logical comparisons.

3. Updating Registers: Results from the execution may be stored in registers or memory, depending on the instruction.

This step is crucial for the overall functioning of the CPU, as it directly affects the outcome of the program being executed.

Address Bus

The address bus is a communication pathway used in computer architecture to transfer addresses from the CPU to other components, such as memory and input/output devices. It determines where data is to be read from or written to in memory. The width of the address bus (number of lines) determines the maximum addressable memory space. For example, a 32-bit address bus can address 2^32 memory locations.

Data Bus

The data bus is a communication system that transfers data between components inside a computer or between computers. It consists of a set of parallel wires or traces that carry data signals. The primary functions of the data bus include:

• Data Transfer: Facilitates the movement of data between the CPU, memory, and peripherals.

• Width: The number of bits it can carry simultaneously (e.g., 8-bit, 16-bit, 32-bit).

• Bidirectional: Allows data to flow in both directions, enabling read and write operations.

Control Bus

The control bus is a communication pathway in a computer's architecture that carries control signals from the control unit to other components. Its primary functions include:

• Coordinating operations: It manages the timing and control of data transfers between the CPU, memory, and input/output devices.

• Signal transmission: It transmits commands such as read, write, and interrupt signals.

• Synchronization: It ensures that all components operate in sync during processing tasks.

Overall, the control bus is essential for the orderly functioning of a computer system.

Cache

A small fast memory that is located close to the CPU, it is there to speed up access to any frequently used data and instructions.

Cache Levels

Cache levels refer to the hierarchy of cache memory in computer architecture, designed to speed up data access. The main levels are:

1. L1 Cache:

   • Location: Closest to the CPU core.

   • Purpose: Stores frequently accessed data and instructions for quick access.

2. L2 Cache:

   • Location: Between L1 and L3, larger than L1.

   • Purpose: Acts as a secondary cache to reduce latency for data not found in L1.

3. L3 Cache:

   • Location: Shared among multiple CPU cores.

   • Purpose: Further reduces access time for data not found in L1 or L2.

Each level increases in size and latency.

Clock

Timing device that generates a continuous signal to synchronize the operations of the processor. It determines the speed at which the CPU executes instructions, measured in hertz (Hz). A higher clock speed allows for more instructions to be processed per second, enhancing overall performance.

Clock Speed Affect on Performance

Clock speed, measured in gigahertz (GHz), indicates how many cycles a CPU can perform per second. Higher clock speeds generally lead to better performance, as the CPU can process more instructions in a given time.

Cores Affect on Performance

The number of cores in a processor affects performance by enabling parallel processing. More cores allow a CPU to handle multiple tasks simultaneously, improving multitasking and performance in multi-threaded applications.

Cache Size Affect on Performance

Cache size significantly impacts performance by influencing data access speed and efficiency. A larger cache can store more data closer to the CPU, reducing the time it takes to retrieve frequently accessed information.

Address Bus Affect on Performance

The address bus affects performance in the following ways:

1. Data Transfer Speed: A wider address bus can access more memory locations simultaneously, increasing data transfer speed.

2. Memory Capacity: A larger address bus allows a system to utilize more RAM, enhancing multitasking and application performance.

3. Latency: A faster address bus reduces the time taken to fetch data from memory, improving overall system responsiveness.

Data Bus Affect on Performance

The data bus affects performance in several ways:

1. Bandwidth: A wider data bus (more bits) allows more data to be transferred simultaneously, increasing throughput.

2. Speed: Higher clock rates of the data bus enable faster data transfer, improving overall system performance.

3. Latency: Shorter data paths reduce the time it takes for data to travel, enhancing responsiveness.

4. Concurrency: Multiple devices can communicate over the bus, improving multitasking capabilities.

Pipelining Affect on Performance

Pipelining enhances performance by allowing multiple instruction phases to overlap in execution. This increases instruction throughput, as the CPU can work on several instructions simultaneously. However, it can introduce complexity and potential hazards, which may require additional cycles to resolve.