LOGICS UT2

ARE MADE UP OF COMBINATIONAL CIRCUITS AND MEMORY ELEMENTS

DIGITAL SYSTEM

TWO-STATE DEVICES THAT ARE USED EXTENSIVELY IN DIGITAL ELECTRONICS

MULTIVIBRATORS

BISTABLE MULTIVIBRATORS ARE CALLED FLIP-FLOPS AND ARE THE BASIC MEMORY DEVICES USED IN SEQUENTIAL ORDER

MULTIVIBRATORS

WHAT ARE THE TWO STATE DEVICES?

ASTABLE AND MONOSTABLE MULTIVIBRATOR

MULTIVIBRATOR THAT SERVES AS AN OSCILLATOR

ASTABLE MULTIVIBRATOR

MULTIVIBRATOR THAT SERVES AS A PULSE SOURCE

MONOSTABLE MULTIVIBRATOR

COMMON NAME GIVE TO TWO-STATE DEVICES

FLIP-FLOP

USE FOR DIGITAL DATA STORAGE AND DIGITAL TRANSFER

FLIP-FLOP

MOST IMPORTANT ELEMENT IN MEMORY

FLIP-FLOP

MEMORY DEVICES THAT IS CAPABLE OF STORING LOGIC 1 AND 0

FLIP-FLOP

FROUP OF FLIPFLOPS CONNECTED TOGETHER

REGISTER

NOT POSSIBLE TO PREDICT THE STARTING STATE OF A FLIP-FLOP

FLIP-FLOP STATE ON POWER-UP

WHAT AFFECTS THE STARTING OF A FLIP-FLOP?

INTERNAL PROPAGATION DELAY, PARASITIC CAPASITANCE, EXTERNAL LOADING

CHANGES STATE EITHER AT THE POSITIVE EDGE OR THE NEGATIVE EDGE OF THE CLOCK PULSE ON CONTROL INPUT

EDGE-TRIGGERED FLIP-FLOP

CONSISTS OF BASIC NOR FF AND TWO AND GATES

CLOCKED SC/SR FLIP-FLOP

CONSTRUCTED FROM TWO SEPARETED FLIP-FLOPS

MASTER-SLAVE FLIP-FLOP

IS THE INTERVAL OF TIME REQUIRE AFTER AN INPUT

PROPAGATION DELAY

IS THE MINIMUM INTERVAL REQUIRED FOR THE LOGIC LEVELS TO BE MAINTAINED CONSTANTLY ON THE INPUTS

SET-UP TIME

ARE THE MINIMUN PULSE WIDTH SPECIFIED BY THE MANUFACTURER FOR CLOCK, SET, CLEAR

HOLD TIME

IS THE HIGHEST RATE THAT A FLIP-FLOP CAN BE TRIGGERED

MAXIMUM CLOCK FREQUENCY

IS THE TOTAL POWER CONSUMPTION OF THE DEVICE

POWER DISSIPATION

NOT CLASSIFIED AS A FLIP-FLOP

SCHMITT TRIGGER DEVICES

HAS ONLY ONE STABLE STATE

MONOSTABLE MULTIVIBRATOR

MULTIVIBRATOR THAT IS ALSO CALLED AS “ONE SHOT”

MONOSTABLE MULTIVIBRATOR

STATE THTA IS FIXED PERIOD OF TIME

QUASI STABLE STATE

WHAT ARE THE TYPES OF ONE SHOTS?

NON-RETRIGGERABLE AND RETRIGGERABLE ONE SHOT

HAS TWO STABLE STATE

CLOCK GENERATOR CIRCUIT

EMPLOYS HIGHLY STABLE AND ACCURATE COMPONENT CALLED QUARTZ CRYSTAL

CRYSTAL CONTROLLED CLOCK GENERATOR

SHIFT REGISTERED FROM ONE FF TO NEXT

SERIAL DATA TRANSFER

TRANSFERRED SIMULTANEOUSLY INTO COUNTER OR TO A REGISTER

PARALLEL DATA TRANSFER

USES FEED BACK WHICH MEANS THE OUTPUT FROM LAST FF IN THE REGISTER IS CONNECTED

SHIFT REGISTER COUNTER

SHIFT REGISTER IS CONNECTED TO THE INPUT OF THE FIRST FF

RING COUNTER

INNVERTED OUTPUTIS CONNECTED TO THE FIST FF INPUT

JOHNSON COUNTER