Systems Architecture

Fetch Stage of FDE cycle

• address is coped from PC to MAR

• PC is incremented

• The instruction at MAR address is read to the RAM

Decode stage of FDE cycle

Instruction in MAR is decoded by CU

Execute stage of FDE cycle

• Data at memory address is read to the RAM

• ALU performs any necessary calculations and stores them in the ACC

• Value in MDR is written to address in MAR

CU

Control Unit

ALU

Arithmetic Logic Unit

ACC

Accumulator

RAM

Random Access Memory

MAR

Memory Address Register

MDR

Memory Data Register

Which cache has the fastest speed

Level 1 cache is the fastest

Which cache has the largest storage

Level 3 cache is the largest

Which cache is the slowest

Level 3 cache are slowest

Which cache has the least storage

Level 1 cache is the smallest

PC

Program Counter

What are registers

Temporary storage for one memory or address

What does the MAR do

holds the address of the current instruction or piece of data to be fetched or stored

What is clock speed

Number of FDE cycles per second

What does 1GHz mean?

1,000,000,000 cycles per second

A dual core can run __ processes simultaneously, whilst a quad core can run ___ processes simultaneously

2

4

What is an embedded system

A computer that is usually a microcontroller designed to complete a specific task and is part of a larger device or system such as a washing machine or a fridge

Embedded systems must be ______ because they cannot be modified once manufactured

reliable