Input/Output

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Computer Organization and Architecture

Last updated 2:57 PM on 5/25/26
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66 Terms

1
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  • Interface to CPU and Memory

  • Interface to one or more peripherals

Input/Output Module

2
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Draw an illustration of a generic model of an I/O Module

ADC → I/O Module

<p>ADC → I/O Module</p>
3
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An external device connected to an I/O Module

Peripheral Device

4
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Suitable for communicating with the computer user

Human readable

5
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Suitable for communicating with equipment

Machine readable

6
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Suitable for communicating with remote devices such as a terminal, a machine-readable device, or another computer.

Communication

7
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Draw an illustration of a block diagram of an external device

knowt flashcard image
8
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What does IRA stand for?

International Reference Alphabet

9
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Coordinates the flow of traffic between internal resources and external devices

Control and Timing

10
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Involves command decoding, data, status reporting, address recognition

Processor Communication

11
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Involves commands, status information, and data

Device Communication

12
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Performs the needed buffering operation to balance device and memory speeds

Data Buffering

13
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Detects and reports transmission errors

Error detection

14
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Draw an illustration of a block diagram of an I/O Module

knowt flashcard image
15
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One of the techniques for I/O operations, where data are exchanged between the processor and the I/O module

Programmed I/O

16
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One of the techniques for I/O operations, where a processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter has completed its work

Interrupt-driven I/O

17
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One of the techniques for I/O operations, where the I/O module and main memory exchange data directly without processor involvement

Direct Memory Access (DMA)

18
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I/O Technique that has no interrupts

Programmed I/O

19
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the two I/O techniques that uses interrupts

Interrupt-driven I/O & Direct Memory Access (DMA)

20
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one of the four I/O Commands,
used to activate a peripheral and tell it what to do

Control

21
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one of the four I/O Commands,
used to test various status conditions associated with an I/O module and its peripherals

Test

22
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one of the four I/O Commands,

causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer

Read

23
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one of the four I/O Commands,

causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral

Write

24
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Draw the flowchart for the Programmed I/O technique

knowt flashcard image
25
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Draw the flowchart for the Interrupt-driven I/O technique

knowt flashcard image
26
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Draw the flowchart for the Direct Memory Access I/O technique

knowt flashcard image
27
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Devices and memory share and address space

Memory-mapped I/O

28
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Separate address spaces

Isolated I/O

29
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Draw the block diagram for Simple Interrupt Processing

knowt flashcard image
30
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Most straightforward approach to the problem. Between the processor and the I/O modules

Multiple interrupt lines

31
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When the processor detects an interrupt, it branches to an interrupt-service routine whose job is to poll each I/O module to determine which module cause the interrupt. Time consuming

Software poll

32
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the interrupt acknowledge line is daisy chained through the modules

daisy chain (hardware poll, vectored)

33
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address of the I/O module or some other unique identifier

Vector

34
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processor uses the vector as a pointer to the appropriate device-service routine, avoiding the need to execute a general interrupt-service routine first

Vectored interrupt

35
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An I/O module must first gain control of the bus before it can raise the interrupt request line

Bus arbitration (vectored)

36
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Draw an illustration of a typical DMA block diagram

Data Count → address register

Data Register ←→ data lines

Address Register → data count

Control Logic

→ Request to DMA

← Acknowledge from DMA

← Interrupt

→ Read

→ Write

<p>Data Count → address register</p><p>Data Register ←→ data lines</p><p>Address Register → data count</p><p>Control Logic</p><p>→ Request to DMA</p><p>← Acknowledge from DMA</p><p>← Interrupt</p><p>→ Read</p><p>→ Write</p>
37
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Draw an illustration of a single-bus, detached DMA

knowt flashcard image
38
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Draw an illustration of a single-bus, integrated DMA-I/O

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39
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Draw an illustration of an I/O bus

knowt flashcard image
40
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8237 DMA

Fly-By DMA Controller

41
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What does DCA stand for?

Direct Cache Access

42
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What chip architecture?

Xeon E5-2600/4600 Chip Architecture

43
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It is transmitted in the form of a sequence of protocol blocks called packets or protocol data units

Network traffic

44
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lowest, or link, level protocol

Ethernet

45
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when was the simplest strategy implemented as a prototype on a number of Intel Xeon processors?

between 2006 and 2010

46
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from the evolution of the I/O function, which order is this?
The CPU directly controls a peripheral device

First (1)

47
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from the evolution of the I/O function, which order is this?

A controller or I/O module is added. The CPU uses programmed I/O without interrupts

Second (2)

48
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from the evolution of the I/O function, which order is this?

Same configuration as in step 2 is used, but now interrupts are employed

Third (3)

49
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from the evolution of the I/O function, which order is this?

The I/O module is given direct access to memory via DMA

Fourth (4)

50
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from the evolution of the I/O function, which order is this?

The I/O module is enhanced to become a processor in its own right, with a specialized instruction set tailored for I/O

Fifth (5)

51
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from the evolution of the I/O function, which order is this?

The I/O module has a local memory of its own and is, in fact, a computer in its own right. With this architecture, a large set of I/O devices can be controlled with minimal CPU involvement

Sixth (6)

52
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It is widely used for peripheral connections

Universal Serial Bus (USB)

53
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Defined a low speed data rate of 1.5 Mbps and a full speed rate of 12 Mbps

USB 1.0

54
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Provides a data rate of 480 Mbps

USB 2.0

55
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Higher speed bus called SuperSpeed in parallel with the USB 2.0 bus

Signaling speed of SuperSpeed is 5 Gbps, but due to signaling overhead the usable data rate is up to 4 Gbps

USB 3.0

56
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Includes a faster transfer mode called SuperSpeed+

USB 3.1

57
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was developed as an alternative to small computer system interface (SCSI) to be used on smaller systems, such as personal computers, workstations, and servers

FireWire Serial Bus

58
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A once common standard for connecting peripheral devices to small and medium-sized computers

Small Computer System Interface (SCSI)

59
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Physical organization is a shared bus, which can support up to ? devices

16 or 32

60
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Most recent and fastest peripheral connection technology to become available for general-purpose use

Thunderbolt

61
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Has become a popular interface for storage area networking and other large storage configurations

InfiniBand

62
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InfiniBand’s first version was released in?

early 2001

63
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High-speed bus system for connecting peripherals of a wide variety of types and speeds

Peripheral Component Interconnect Express (PCI Express)

64
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An interface for disk storage systems. Widely used in desktop computers and in industrial and embedded applications

Serial Advance Technology Attachment (SATA)

65
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Has become essential for supporting personal computers, workstations, servers, and massive data storage devices in organizations large and small

Ethernet

66
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Now connects computers, tablets, smart phones, and other electronic devices such as video cameras TVs and thermostats

Wi-Fi