A Flat-Gain 255–315 GHz Power Amplifier in 130 nm Advanced SiGe BiCMOS

Vocabulary flashcards covering key concepts, parameters, matching networks, and measured performance from the J-band flat-gain power amplifier lecture notes.

IHP 130-nm BiCMOS Technology

The advanced semiconductor process node used to fabricate the power amplifier, featuring experimental $f_T$ of $470\,\text{GHz}$ and $f_{max}$ of $650\,\text{GHz}$ with an aluminum back-end-of-line (BEOL).

PA Unit Topology

A pseudo-differential cascode common-emitter amplifier stage used as the basic gain block within each stage of the power amplifier.

Quiescent Collector Current Density ($I_{CQ}$)

Set to $3.5\,\text{mA/finger}$ targeting the peak transistor $f_T / f_{max}$ performance.

HBT Emitter Area

Selected as $8 \times (0.12 \times 0.9)\,\mu\text{m}^2$ for devices $Q_{1\text{-}4}$ based on load-pull simulations targeting a saturated output power ($P_{sat}$) of greater than $10\,\text{dBm}$.

Optimum Collector-Emitter Voltage ($V_{CEQ1OPT}$)

The optimum voltage headroom for the lower common-emitter transistors ($Q_1/Q_2$) that guarantees full utilization of the supply voltage without causing early compression before the cascode devices ($Q_3/Q_4$), thereby maximizing collector efficiency ($\eta_c$).

MN1 (Input Matching Network)

An input matching network designed as a $\pi$-network ($C\text{-}L\text{-}C$) optimized for wideband input conjugate matching centered at $275\,\text{GHz}$.

MN2 (Interstage Matching Network)

An interstage matching network optimized to conjugately match Stage 1 and Stage 2 at $310\,\text{GHz}$ to stagger the gain response.

MN3 (Interstage Matching Network)

An interstage matching network designed to split power equally two ways while conjugately matching Stage 2 and Stage 3 at around $270\,\text{GHz}$.

MN4 (Output Matching Network)

The final stage output matching network optimized specifically for maximum output power load pull at $285\,\text{GHz}$, excluded from the interstage gain-staggering technique.

Open Stub TL6

A transmission line element used in MN2 instead of a shunt MIM capacitor to prevent susceptibility to modeling errors and process variations associated with extremely small capacitance values.

Marchand Balun

An on-chip passive component used at the differential input and output ports to enable single-ended on-wafer S-parameter and power measurements.

Peak Saturated Output Power ($P_{sat}$)

The maximum measured saturated output power achieved by the PA, equal to $15.5\,\text{dBm}$ at $255\,\text{GHz}$.

Peak Collector Efficiency ($\eta_c$)

The maximum measured collector power efficiency of the fabricated PA, reaching $5.5\%$ at $255\,\text{GHz}$.

Small-Signal Gain and Flatness

Achieved performance displaying a small-signal gain of $20\,\text{dB}$ with a gain response flatness of $\pm 0.6\,\text{dB}$ across the band from $255\,\text{GHz}$ to $315\,\text{GHz}$.

PA Core Area

The physical silicon area occupied by the 3-stage two-way power amplifier core, measuring $0.16\,\text{mm}^2$ (excluding baluns and pads).