assembly

2 parts of a CPU

datapath + control unit

2 parts of a datapath

ALU + registers

purpose of control unit

• sends signals to CPU components

• determined based off PC and status register values

what is a word

addressable cell of fixed size

how is RAM measured

length x width

• length is number of words

• width is how many bits in a word

2 methods of connecting I/O to CPU

1. memory mapped: devices act like memory from CPU POV with its own address in memory

2. instruction mapped: CPU has specific instructions for the device

what is a bus

array of wires simultaneously converting 1 bit along 1 line

2 types of buses

1. point to point: connect 2 components

2. multipoint: connect many components (data bus)

functions of data, control and address lines

data line: convey bits from one component to another

control line: choose direction of data flow + when devices can access the bus

address line: choose data source + destination location

• one way

equation for cpu time to run a program

T = seconds/program = instructions/program x avg cycles/instruction x seconds/cycle

MARIE specs (6)

• twos complement binary

• von neumann (fixed word length data + instructions)

• 16 bit word size, 16 bit instructions (4 opcode, 12 address)

• 16 bit ALU

• 7 registers

ACC

holds data to be processed

• 16 bit

MBR

holds data just read from memory/to be written to memory next

• 16 bit

IR

holds instruction just before execution

• 16 bit

MAR

holds memory address of data being referenced

• 12 bit

PC

holds address of next instruction to be executed

• 12 bit

IN

holds data read from input device

• 8 bit

OUT

holds data to be written to output device

• 8 bits

which registers are the 2 special bus connection in between in MARIE

• AC + MBR

• ALU + AC + MBR

load X

loads contents of address X into AC

• MAR ← X

• MBR ← M[MAR]

• AC ← MBR

store X

stores contents of AC at address X

• MAR ← X + MBR ← AC

• AC ← MBR

add x

adds contents of address X to AC

• MAR ← X

• MBR ← M[MAR]

• AC ← AC + MBR

subt X

subtracts contents of address X from AC

• MAR ← X

• MBR ← M[MAR]

• AC ← AC - MBR

input

inputs into AC

• AC ← InREG

output

outputs value in AC

• AC ← OutREG

skipcond

skips next instruction

• if IR[11 - 10] = 00 and AC < 0 then

  • PC ← PC + 1

• else if IR[11 - 10] = 01 and AC = 0 then

  • PC ← PC + 1

• else if IR[11 - 10] = 10 and AC > 0 then

  • PC ← PC + 1

jump X

load X into PC

• PC ← X

FDE cycle

1. fetch from memory

• address from PC —> IR

• instruction from MAR —> IR

• increment PC

2. decode

• address put into MAR

• if operand uninvolved put in MBR

• else data in MAR —> MBR

3. exectute

6 step interrupt processing

1. store register data in memory

2. look up ISR address in interrupt table

3. place ISR address in PC

4. execute ISR instructions

5. restore registers data

6. resume FDE

maskable/non-maskable interrupt

maskable: interrupts ignored while another interrupt is running

non-maskable: must be processed to keep system stable ssmblera

assembler process

• create object program file from source code

1. assembler assembles as much as possible while building symbol table with memory references for symbols

2. instructions completed using symbol table

AddI

MAR ← X

MBR ← M[MAR]

MAR ← MBR

MBR ← M[MAR]

AC ← AC + MBR

JnS

MBR ← PC

MAR ← X

M[MAR] ← MBR

MBR ← X

AC ← 1

AC ← AC + MBR

PC ← AC

JumpI

MAR ← X

MBR ← M[MAR]

PC ← MBR

clear

AC ← 0