RTL Design and Verilog Architecture Vocabulary

Vocabulary flashcards covering System Architecture, RTL Design, Verilog modeling styles, assignments, testbenches, Finite State Machines, and delay types based on lecture notes.

System Architecture Team

A critical group in chip development that defines and shapes the high-level structure and functionality of an SoC, bridging end-product requirements with detailed implementation.

RTL Design

Register-Transfer-Level design; a method of describing digital circuits in terms of data flow between registers and the logical operations performed on that data.

Linting

The practice of using automated code analysis tools to catch syntax mistakes, enforce formatting standards, and prevent potential bugs early in the design flow.

Synthesis

The process of transforming high-level RTL code into real logic hardware, converting statements into logic gates and flip-flops while adhering to timing, area, and power constraints.

Design for Testability (DFT)

The technique of adding dedicated test logic and scan chains into a chip design to detect physical manufacturing defects such as stuck-at faults or short circuits.

Verilog

A Hardware Description Language (HDL) used to model, simulate, and design digital logic systems across various levels of abstraction.

Behavioral Modeling

A high-level Verilog modeling style that uses procedural constructs to describe how a circuit behaves rather than detailing its specific hardware gates.

Dataflow Modeling

A Verilog modeling style that describes how data moves between signals using continuous assignments and logical equations.

Structural Modeling

A Verilog modeling style that describes a system as an explicit schematic-like network of interconnected sub-modules and logic gates.

initial Block

A Verilog procedural block that executes exactly once starting at time $t=0$, commonly used in testbenches for signal initialization.

always Block

A Verilog procedural construct that loops continuously throughout simulation, executing its body whenever triggered by an event defined in its sensitivity list.

Sensitivity List

A specified list of signals or events in an always block header that triggers execution of the procedural code inside whenever a signal value changes.

Continuous Assignment

A statement written with the assign keyword outside procedural blocks that continuously drives a value onto a wire net whenever right-hand operands change.

Blocking Assignment

A procedural assignment represented by the $=$ operator that executes sequentially line-by-line within an always block, evaluating and updating variables immediately.

Non-Blocking Assignment

A procedural assignment represented by the $<=$ operator where all expressions are evaluated concurrently without delaying execution of subsequent lines, primarily used for sequential logic.

Verilog Testbench

A non-synthesizable simulation environment containing a stimulus generator, DUT instantiation, and output checking mechanism to verify circuit functionality.

Mealy Machine

A Finite State Machine (FSM) architecture where the output signals are determined by a combination of both the present state and current input values.

Moore Machine

A Finite State Machine (FSM) architecture where output values depend exclusively on the present state, independent of immediate input changes.

Inertial Delay

A physical logic gate delay model where input pulses shorter than the specified delay duration are filtered out and fail to propagate to the output.

Intra-Assignment Delay

A timing control syntax (e.g., $a = \#5\,b$) where the right-hand side expression is evaluated immediately, but the assignment to the left-hand variable is delayed by the specified time.