Computer Architecture and Memory Basics (Flashcards)

Vocabulary flashcards covering key terms and definitions from the notes on computer architecture, memory, caching, virtual memory, processors, and I/O buses.

Assembly language

A low-level human-readable representation of machine instructions that helps understand what the processor does behind the scenes.

Linker

A tool that combines object files and libraries into a single executable.

Loader

Loads an executable from storage into memory and prepares it to run on the CPU.

Dynamic linking

Linking libraries at runtime so multiple programs can share common libraries.

Bus

A data pathway that connects CPU, memory, and peripherals to transfer information.

Peripheral bus

A bus that connects input/output devices to the processor and memory.

Memory bus

A data pathway that moves information between RAM and the CPU.

System bus

The collection of buses that interconnect major components of a computer.

Main memory (RAM)

Fast, volatile storage used by the CPU for active data and instructions.

Secondary memory

Non-volatile storage such as SSDs/HDDs used for long-term data.

Cache memory

Small, fast memory near the CPU that stores copies of frequently used data.

Level 1 Cache (L1)

The smallest, fastest cache closest to the cores.

Level 2 Cache (L2)

Larger than L1 but slower; often per-core or shared.

Level 3 Cache (L3)

Largest cache, shared across cores and slower than L1/L2.

Cache miss rate

Frequency at which data requested is not in cache, causing slower access.

Processor (CPU)

The brain of the computer that fetches, decodes, and executes instructions.

Fetch

Obtaining the next instruction from memory.

Decode

Translating a fetched instruction into signals for execution.

Execute

Performing the operation specified by an instruction.

Write-back

Storing the result of an instruction to registers or memory.

Arithmetic Logic Unit (ALU)

CPU unit that performs arithmetic and logical operations.

Control Unit (CU)

Decodes instructions and coordinates data flow and operations.

Processing Unit (PU)

Processing unit; the core component handling instruction processing.

Register

Small, fast storage inside the CPU for data/addresses during processing.

Program Counter (PC)

Register that holds the address of the next instruction to fetch.

Memory Address Register (MAR)

Holds the memory address to be read or written.

Memory Buffer Register (MBR)

Holds data being transferred to/from memory.

Current Instruction Register (CIR)

Temporary register that holds the instruction just fetched.

Vector addition

Adding corresponding elements of two vectors (SIMD concept).

Vector Length (VL)

Number of elements in a vector.

Number of lanes (KL)

Parallel processing lanes used in vector operations.

64-bit lane

Each lane processes 64 bits of data in parallel.

Virtual memory

Technique using disk space to extend RAM, creating a larger address space.

Memory Management Unit (MMU)

Hardware that translates virtual addresses to physical addresses and enforces protection.

Paging

Swapping pages between RAM and disk to free memory.

Swapping

Transferring memory pages between RAM and disk as needed.

Segment tables

Structures that track memory segments (text, data, stack, heap) for mapping.

Page tables

Structures that map virtual pages to physical frames.

Process

An active running instance of a program.

Program

A set of instructions stored on storage media.

Isolation/Protection

Mechanisms ensuring processes cannot access each other’s memory.

Multicore CPU

CPU with multiple cores on one chip enabling parallel execution.

Interrupt Descriptor Table (IDT)

Table that directs how the CPU handles different interrupt types.

Interrupt

Signal from hardware or software requesting CPU attention.

PCI Express (PCIe)

High-speed serial bus linking CPU to devices with lanes for data transfer.

Thunderbolt

High-speed interface combining PCIe and DisplayPort with daisy-chaining.

Direct Memory Access (DMA)

Allows devices to transfer data directly to memory without CPU intervention.

DMA controller

Hardware that manages DMA transfers.

Programmed I/O (PIO)

CPU-driven I/O where the CPU manages data transfers.

Daisy chain

Connecting multiple devices in series on a bus.