MOS VLSI Circuit Design Lecture Notes

This collection of flashcards covers key terms and concepts from the MOS VLSI Circuit Design lecture notes, providing definitions and explanations relevant to semiconductor fabrication and circuit design.

Fabrication Process

The process that links circuit design, chip performance, and manufacturing parameters.

MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor, a type of transistor used for amplifying or switching electronic signals.

Insulators

Materials that do not conduct electricity.

Conductors

Materials that allow the flow of electrical current.

Semiconductors

Materials that have electrical conductivity between insulators and conductors.

Dopants

Impurities added to semiconductor materials to change their electrical properties.

n-type

Silicon doped with Group V elements to create extra electrons as charge carriers.

p-type

Silicon doped with Group III elements to create holes as charge carriers.

Single Crystal Growth

The process of pulling a small seed crystal from molten silicon to create boules.

Wafers

Flat circular disks of silicon used to build MOS transistors.

Photolithography

A process used in semiconductor fabrication to transfer a pattern onto a layer on the chip.

Photoresist

A light-sensitive material used to form a patterned coating on a surface.

Etching

A process to remove material from the surface of a wafer during manufacturing.

Oxidation

The process that creates a silicon dioxide (SiO2) layer on the silicon surface.

Metallization

The process of building metal interconnections between devices.

CMOS Process

A technology for fabricating both pMOS and nMOS transistors on the same silicon substrate.

LOCOS

LOCal Oxidation of Silicon, a technique for device isolation in semiconductor fabrication.

Vias

Electrical connections between different metal layers in a multilayer chip.

Minimum-size Inverter

A fundamental CMOS circuit with specific dimension constraints to optimize area and performance.

Silicon on Insulator (SOI)

A fabrication technique that places transistors on an insulating material, reducing parasitic capacitance.