1.1.1 Architecture of the CPU - GCSE OCR Computer Science

stored program concept

programs and data are stored together in RAM (primary storage)

CPU

Central Processing Unit, the brains of the computer where all processing happens, actions taken and data transformed

ALU

- Arithmetic Logic unit
- performs execute phase and all logical, arithmetic, and binary shift operations

CU

- Control Unit
- controls fetch-execute cycle
- coordinates instruction fetching from Ram, decoding and execution

registers

- single memory that holds instructions for f-e cycle
- has faster read-write speed than any other memory

cache

- primary storage that holds recent and frequently used algorithms and data

order cache, RAM and registers by their read-write speed (fastest to slowest)

registers, cache, RAM

how does cache size affect processing speed?

larger cache makes processing faster as there is a higher chance of algorithms and data being stored in it so they can be retrieved faster

level 1 cache

smallest (under 1MB) with fastest r-w speed

level 2 cache

larger than L1 cache with slower r-w speed

level 3 cache

highest capacity cache, may be on motherboard instead of in CPU

Von Neumann architecture

general computer architecture using stored program concept

general purpose register

used by programmers

special purpose registers

have specific uses within the f-e cycle

MAR

memory address register, stores address to be read/written to primary storage

MDR

memory data register, stores data to be read/written to primary storage

what do the MAR and MDR do together?

they store everything and allow the CPU and RAM to communicate

what is unique about the MAR and MDR?

they are the only registers that can communicate with the RAM

ACC

accumulator, stores results of all calculations done by the ALU

PC

program counter, contains address of next instruction to be fetched and is incremented after each fetch phase

why does the PC need to be incremented?

so the correct instruction is fetched in the next fetch phase

CIR

current instruction register, holds instruction currently being executed

steps of the fetch phase

1. instructions are stored at a specific memory address
2. address copied from PC to MAR
3. CU fetches data from address and copies it to MDR
4. instruction moved to CIR
5. PC is incremented

what are the components used in the fetch phase? (in order)

PC, MAR, CU, MDR, CIR, PC

decode phase

CU decodes instruction from MDR/CIR

execute phase

decodes instruction is executed and the next f-e cycle begins

bus

carry addresses, signals and data between the CPU and RAM

address bus

carries address being read from/written to the CPU (MAR) to RAM

data bus

carries data being read from/written to CPU between the MDR and RAM

control bus

carries the signal telling the RAM to read/write between the CPU and RAM

operation

command to be run

operand

data needed for the command