CPU Architecture and the Von Neumann Model

These flashcards cover CPU architecture, including the Von Neumann model, internal components, registers, system buses, performance factors, ports, and the Fetch-Execute cycle.

Von Neumann Model

A computer architecture developed in the mid-1940s by John Von Neumann that introduced the concept of the stored program computer, where both instructions and data are stored together in memory.

Arithmetic Logic Unit (ALU)

A CPU component that performs arithmetic and logic operations, utilizing the Accumulator ($ACC$) as a temporary register for calculations.

Control Unit (CU)

The component of the CPU that fetches and decodes instructions from memory and sends control signals via the control bus to coordinate and synchronize operations.

System Clock

Generates regular timing signals for synchronization; defined by the clock cycle, which is the time interval for one basic operation (e.g., $3.5\,\text{GHz}$).

Immediate Access Store (IAS)

Temporary memory ($RAM$) holding programs and data currently needed by the CPU, which is much faster than backing storage like an $HDD$.

Current Instruction Register (CIR)

A special-purpose register that holds the specific instruction currently being decoded or executed by the CPU.

Program Counter (PC)

A register that holds the address of the next instruction to be fetched from memory.

Memory Address Register (MAR)

A register that stores the address of the memory location that the CPU needs to read from or write to.

Memory Data Register (MDR)

Also known as the Memory Buffer Register ($MBR$), it stores the actual data read from or written to the memory location specified in the $MAR$.

Index Register (IX)

A CPU register specifically used in the process of indexed addressing.

Status Register (SR)

A register that holds various flags indicating the current state of the CPU.

Address Bus

A unidirectional bus that carries memory addresses from the CPU to memory or $I/O$ devices; its width determines the maximum addressable memory (e.g., a $32$-bit bus addresses $2^{32}$ locations).

Data Bus

A bidirectional bus that transfers data and instructions between the CPU and other components; its width corresponds to the computer's word length.

Control Bus

A bidirectional bus that carries control, timing, and interrupt signals to manage various computer operations.

Cache Memory

Small, high-speed memory located close to the CPU ($SRAM$) that stores frequently used data and instructions to reduce access time to main memory ($DRAM$).

Multi-core Processors

Processors containing multiple cores each with its own $ALU$, $CU$, and registers, allowing for parallel processing.

Asynchronous Serial Data Transmission

A data transfer method used by $USB$ where bits are sent one at a time along a single wire without a shared clock, using start and stop bits for framing.

HDMI (High-Definition Multimedia Interface)

A high-bandwidth digital interface that carries audio and video signals, supporting features like $120\,\text{Hz}$ refresh rates and $10\,\text{Gbps}$ transfer rates.

VGA (Video Graphics Array)

An outdated analogue video connection introduced in the late 1980s that supports limited resolutions and colors (e.g., $640 \times 480$ pixels).

Fetch-Execute Cycle

The continuous three-step process (Fetch, Decode, Execute) by which the CPU retrieves and runs instructions from memory.

Register Transfer Notation (RTN)

A shorthand notation used to describe the movement of data between registers, such as $MAR \leftarrow [PC]$ or $MDR \leftarrow [[MAR]]$.

Interrupt

A signal from hardware or software that causes the CPU to pause its current task, save its state, and run an Interrupt Service Routine ($ISR$).