ici 1+2+3

What is the main reason for the exponential growth of digital IC complexity?

A. Reduced transistor count

B. Manufacturing advancements and higher integration needs

C. Lower memory usage

D. Smaller software size

: B. Manufacturing advancements and higher integration needs

What is one major challenge in modern VLSI system development?

A. Lack of programming languages

B. Managing design complexity

C. Limited logic gates

D. Small chip size

: B. Managing design complexity

Which of the following is NOT a major VLSI activity?

A. Fabrication

B. Packaging

C. Testing

D. Web development

: D. Web development

Which chip type generally has higher complexity than memory chips?

A. Analog chips

B. Sensor chips

C. Logic chips

D. Power chips

: C. Logic chips

Which design style provides the highest performance and smallest area?

A. FPGA

B. Standard-cell design

C. Full-custom design

D. Gate array

: C. Full-custom design

What is a disadvantage of full-custom design?

A. Low flexibility

B. Long design time and high cost

C. Poor performance

D. Large chip area

: B. Long design time and high cost

Which semi-custom design style supports faster deployment?

A. Full-custom design

B. FPGA

C. Manual layout design

D. Transistor-level design

: B. FPGA

New VLSI technology generations typically appear every:

A. 10 years

B. 5 years

C. 2 years

D. 20 years

: C. 2 years

What happens when device dimensions become smaller?

A. Lower integration density

B. Reduced performance

C. Higher integration density

D. Increased package size

: C. Higher integration density

Which model is commonly used to represent VLSI design?

A. Waterfall model

B. Spiral model

C. Y-Chart

D. OSI model

: C. Y-Chart

Which domain describes what the system does?

A. Physical domain

B. Behavioral domain

C. Structural domain

D. Geometrical domain

: B. Behavioral domain

Which level belongs to the behavioral domain?

A. Routing

B. Placement

C. Finite State Machine

D. Mask layout

: C. Finite State Machine

Which domain focuses on hardware implementation?

A. Structural domain

B. Behavioral domain

C. Physical domain

D. Timing domain

: A. Structural domain

RTL stands for:

A. Register Timing Logic

B. Routing Transfer Layer

C. Register Transfer Level

D. Reduced Timing Layout

: C. Register Transfer Level

Which stage belongs to the physical domain?

A. FSM design

B. Algorithm design

C. Placement

D. Architecture definition

: C. Placement

What is the final output of the physical design process?

A. Source code

B. Algorithm

C. Geometrical layout

D. Test vectors

: C. Geometrical layout

Why is verification important in VLSI design?

A. To increase software size

B. To avoid redesign cost and delays

C. To reduce transistor count

D. To simplify programming

: B. To avoid redesign cost and delays

Which design approach starts from system architecture?

A. Bottom-up

B. Top-down

C. Random design

D. Physical-first design

: B. Top-down

What is the main advantage of bottom-up design?

A. Good design control

B. Easier debugging

C. Uses lower-level feasibility information

D. Faster fabrication

: C. Uses lower-level feasibility information

Hierarchical decomposition improves:

A. Noise only

B. Design clarity and modularity

C. Packaging size

D. PCB color

: B. Design clarity and modularity

A floorplan mainly defines:

A. Software modules

B. Testing speed

C. Placement of blocks

D. Power supply type

: C. Placement of blocks

Which strategy is commonly used in hierarchical VLSI design?

A. Divide and conquer

B. Trial and error

C. Waterfall coding

D. Random routing

: A. Divide and conquer

What is the purpose of carry-lookahead logic?

A. Reduce memory usage

B. Improve carry computation speed

C. Increase transistor size

D. Simplify PCB design

: B. Improve carry computation speed

What does regularity mean in VLSI design?

A. Using different blocks everywhere

B. Repeating similar structures

C. Avoiding hierarchy

D. Increasing routing length

: B. Repeating similar structures

Which is a benefit of regularity?

A. Increased verification effort

B. Simplified design and layout

C. Lower scalability

D. More complex routing

: B. Simplified design and layout

What is modularity in system design?

A. Designing without interfaces

B. Using independent functional modules

C. Removing hierarchy

D. Increasing transistor count

: B. Using independent functional modules

One advantage of modularity is:

A. Difficult integration

B. Parallel development

C. Longer routing delay

D. Reduced reuse

: B. Parallel development

What is the main goal of locality?

A. Increase global interconnections

B. Minimize long-distance interconnections

C. Increase chip size

D. Remove routing channels

: B. Minimize long-distance interconnections

Which benefit results from locality?

A. Reduced interconnect delay

B. Larger chip area

C. Lower scalability

D. More timing errors

: A. Reduced interconnect delay

FPGA stands for:

A. Fast Programmable Gate Architecture

B. Field Programmable Gate Array

C. Functional Processing Gate Array

D. Flexible Physical Gate Array

: B. Field Programmable Gate Array

Which component is a key part of FPGA architecture?

A. CLB

B. DRAM bank only

C. Heat sink

D. PCB connector

: A. CLB

CLB in FPGA commonly contains:

A. Mechanical switches

B. LUTs and flip-flops

C. CPUs only

D. Optical sensors

: B. LUTs and flip-flops

What language is commonly used for FPGA behavioral description?

A. HTML

B. SQL

C. Verilog

D. CSS

: C. Verilog

Which is an advantage of FPGA design?

A. No customization possible

B. Fast turnaround time

C. Highest ASIC performance

D. Lowest chip cost always

: B. Fast turnaround time

Gate Array customization mainly uses:

A. Plastic packaging

B. Metal mask interconnections

C. Software patches

D. Optical fibers

: B. Metal mask interconnections

Compared to FPGA, Gate Array generally offers:

A. Lower speed

B. Higher speed

C. No routing

D. No customization

: B. Higher speed

What is the Sea-of-Gates concept?

A. Routing over active cell areas

B. Removing routing layers

C. Using water cooling

D. Replacing transistors with memory

: A. Routing over active cell areas

Standard-cell design uses:

A. Hand-drawn transistors only

B. Pre-designed logic cell libraries

C. Mechanical relays

D. Analog-only circuits

: B. Pre-designed logic cell libraries

Why are standard cells available in multiple sizes?

A. Decoration purposes

B. Trade-off between speed, power, and area

C. Reduce routing channels

D. Simplify packaging

: B. Trade-off between speed, power, and area

Which item is included in cell characterization?

A. Timing simulation models

B. Web APIs

C. Operating systems

D. Mechanical dimensions only

: A. Timing simulation models

What surrounds the standard-cell chip core?

A. Heat sink

B. I/O frame

C. Battery pack

D. Cooling fan

: B. I/O frame

Placement and Routing (P&R) must consider:

A. Weather conditions

B. Timing and area constraints

C. Programming language syntax

D. PCB color

: B. Timing and area constraints

Full-custom design provides:

A. Minimal control over layout

B. Maximum performance optimization

C. No transistor sizing

D. Lowest design complexity

: B. Maximum performance optimization

Which metric is NOT part of design quality?

A. Reliability

B. Manufacturability

C. Testability

D. Screen resolution

: D. Screen resolution

What is yield in chip manufacturing?

A. Chip operating frequency

B. Percentage of functional chips

C. Number of engineers

D. Amount of routing layers

: B. Percentage of functional chips

What is an important requirement for testability?

A. Random transistor sizing

B. Effective test vectors

C. Larger packaging

D. Fewer logic gates

: B. Effective test vectors

Manufacturability focuses on:

A. Software debugging

B. Reliable large-scale production

C. PCB painting

D. Operating systems

: B. Reliable large-scale production

Which issue can affect chip reliability?

A. Hot-carrier degradation

B. Web latency

C. Audio distortion

D. Low internet speed

: A. Hot-carrier degradation

What is the purpose of ESD protection?

A. Improve graphics quality

B. Protect I/O circuits

C. Increase routing area

D. Reduce memory size

: B. Protect I/O circuits

Technology updateability helps:

A. Increase redesign cost

B. Adapt designs to new technologies

C. Remove CAD tools

D. Reduce functionality

: B. Adapt designs to new technologies

Question 1

What does MOS stand for?

A. Metal Oxide Semiconductor

B. Metal Optical System

C. Micro Oxide Silicon

D. Main Operating System

: A. Metal Oxide Semiconductor

Question 2

Which layer in a MOS structure acts as an insulator?

A. Metal gate

B. Silicon substrate

C. SiO₂ layer

D. Drain region

: C. SiO₂ layer

Question 3

In a basic MOS structure, the substrate is commonly:

A. n-type silicon

B. p-type silicon

C. metal

D. polysilicon

: B. p-type silicon

Question 4

What happens in accumulation mode of a MOS capacitor?

A. Holes are attracted to the surface

B. Electrons are attracted to the surface

C. Depletion region disappears

D. Drain current increases

: A. Holes are attracted to the surface

Question 5

A negative gate voltage applied to a p-type substrate causes:

A. inversion

B. depletion

C. accumulation

D. saturation

: C. accumulation

Question 6

In depletion mode operation, majority carriers are:

A. attracted to the surface

B. repelled from the surface

C. converted into electrons

D. unchanged

: B. repelled from the surface

Question 7

Which region forms when the surface becomes n-type?

A. depletion region

B. inversion layer

C. oxide layer

D. body region

: B. inversion layer

Question 8

The conducting channel in an NMOS transistor is formed by:

A. holes

B. ions

C. electrons

D. photons

: C. electrons

Question 9

The source and drain regions in an NMOS are usually:

A. p+ regions

B. intrinsic regions

C. n+ regions

D. oxide regions

: C. n+ regions

Question 10

The MOSFET terminal used to control the channel is:

A. drain

B. source

C. substrate

D. gate

: D. gate

Question 11

Which MOSFET type has no conducting channel at zero gate bias?

A. depletion-mode MOSFET

B. enhancement-mode MOSFET

C. JFET

D. bipolar transistor

: B. enhancement-mode MOSFET

Question 12

What does VT represent in MOSFET operation?

A. transition voltage

B. threshold voltage

C. thermal voltage

D. transfer voltage

: B. threshold voltage

Question 13

When VGS < VT, the MOSFET operates in:

A. saturation region

B. linear region

C. cutoff region

D. inversion region

: C. cutoff region

Question 14

When VGS > VT, a MOSFET channel is:

A. destroyed

B. disconnected

C. formed

D. reversed

: C. formed

Question 15

Which parameter mainly controls MOSFET drain current?

A. gate voltage

B. oxide color

C. substrate thickness

D. package type

: A. gate voltage

Question 16

In the linear region, drain current ID is approximately proportional to:

A. VT

B. VDS

C. Cox

D. tox

: B. VDS

Question 17

The MOSFET behaves like a voltage-controlled:

A. capacitor

B. current source

C. resistor

D. inductor

: C. resistor

Question 18

Pinch-off occurs when:

A. VGS = 0

B. VDS = 0

C. VDS = VGS − VT

D. VSB = 0

: C. VDS = VGS − VT

Question 19

After pinch-off, the MOSFET enters:

A. cutoff region

B. saturation region

C. accumulation mode

D. depletion mode

: B. saturation region

Question 20

Which region absorbs most excess voltage after pinch-off?

A. source region

B. oxide layer

C. depleted region near drain

D. substrate contact

: C. depleted region near drain

Question 21

The body effect causes threshold voltage to:

A. decrease only

B. increase with VSB

C. become zero

D. remain constant

: B. increase with VSB

Question 22

The body effect coefficient is represented by:

A. λ

B. μn

C. γ

D. Cox

: C. γ

Question 23

Which symbol represents oxide capacitance per unit area?

A. Cox

B. Cgs

C. Cgd

D. Csb

: A. Cox

Question 24

In an NMOS transistor, the substrate bias coefficient γ is usually:

A. negative

B. zero

C. positive

D. infinite

: C. positive

Question 25

Channel length modulation mainly affects:

A. threshold voltage

B. oxide thickness

C. saturation current

D. gate resistance

: C. saturation current

Question 26

The channel-length modulation parameter is:

A. β

B. λ

C. γ

D. α

: B. λ

Question 27

Increasing VDS in saturation slightly increases ID because of:

A. body effect

B. punch-through

C. channel-length modulation

D. inversion

: C. channel-length modulation

Question 28

Which operation region is also called triode region?

A. cutoff

B. linear

C. saturation

D. inversion

: B. linear

Question 29

In saturation mode, MOSFET current ideally depends mainly on:

A. VGS

B. VDS

C. substrate resistance

D. temperature only

: A. VGS

Question 30

The gradual channel approximation assumes:

A. Ex > Ey

B. Ey > Ex

C. Ex = Ey

D. no electric field exists

: B. Ey > Ex

Question 31

Short-channel effects occur when:

A. channel length is very large

B. oxide is removed

C. channel length becomes comparable to depletion width

D. VGS = 0

: C. channel length becomes comparable to depletion width

Question 32

Velocity saturation occurs because carriers reach:

A. cutoff voltage

B. maximum drift velocity

C. oxide boundary

D. inversion thickness

: B. maximum drift velocity

Question 33

Reducing channel length generally causes VT to:

A. increase

B. remain constant

C. decrease

D. become negative always

: C. decrease

Question 34

Which effect causes threshold voltage reduction in short-channel devices?

A. charge sharing

B. accumulation

C. oxide tunneling

D. overlap capacitance

: A. charge sharing

Question 35

Narrow-channel effect causes threshold voltage to:

A. decrease

B. increase

C. remain unchanged

D. become zero

: B. increase

Question 36

DIBL stands for:

A. Drain-Induced Barrier Lowering

B. Drain Interface Bulk Loading

C. Dynamic Inversion Bias Level

D. Diffusion Induced Body Loss

: A. Drain-Induced Barrier Lowering

Question 37

Subthreshold conduction occurs when:

A. VGS > VDD

B. VGS < VT

C. VDS = 0

D. body terminal disconnected

: B. VGS < VT

Question 38

Hot-carrier effect is mainly caused by:

A. low electric field

B. high electric field

C. oxide thickness increase

D. low temperature

: B. high electric field

Question 39

Which scaling method keeps electric field approximately constant?

A. constant-voltage scaling

B. full scaling

C. narrow scaling

D. thermal scaling

: B. full scaling

Question 40

In full scaling, device dimensions are reduced by:

A. S²

B. S³

C. S

D. 1/S²

: C. S

Question 41

In constant-voltage scaling, supply voltage:

A. decreases

B. increases

C. remains unchanged

D. becomes zero

: C. remains unchanged

Question 42

MOSFET gate capacitance affects:

A. switching delay

B. package color

C. oxide purity only

D. substrate type only

: A. switching delay

Question 43

In cutoff mode:

A. Cgs = Cgd = 0

B. Cgs is maximum

C. Cgd is negative

D. Cgb is zero

: A. Cgs = Cgd = 0

Question 44

In saturation mode:

A. Cgd is large

B. Cgs ≈ (2/3)CoxWL

C. Cgb is maximum

D. all capacitances are equal

: B. Cgs ≈ (2/3)CoxWL

Question 45

Overlap capacitance exists because of:

A. gate overlap with source/drain

B. substrate contact

C. body effect

D. inversion charge

: A. gate overlap with source/drain

Question 46

The actual channel length is approximately:

A. L = LM + 2LD

B. L = LM − 2LD

C. L = LD − LM

D. L = 2LM

: B. L = LM − 2LD

Question 47

Junction capacitance is mainly associated with:

A. pn junction depletion region

B. oxide layer

C. gate metal

D. inversion channel only

: A. pn junction depletion region

Question 48

Which capacitance changes with applied voltage?

A. fixed capacitance

B. ideal capacitance

C. voltage-dependent junction capacitance

D. overlap capacitance only

: C. voltage-dependent junction capacitance

Question 49

MOSFET parasitic capacitances mainly influence:

A. DC gain only

B. propagation delay

C. package size

D. transistor color

: B. propagation delay

Question 50

Which statement about MOSFET is correct?

A. Current flows without inversion

B. MOSFET is current-controlled

C. MOSFET is voltage-controlled

D. Gate current is always large

: C. MOSFET is voltage-controlled