COMP1860 Lecture 7.1 Building our Digital World: Computer Systems & Architecture

Flashcards covering key vocabulary and concepts from the lecture.

Von Neumann Architecture

Data and instructions are stored in a single read–write memory, memory is addressable by location, and instructions execute sequentially unless explicitly modified.

Instruction Interpreter

One of two components that constitute the CPU, along with the Arithmetic and Logic Module.

Arithmetic and Logic Module

One of two components that constitute the CPU, along with the Instruction Interpreter.

MAR (Memory Address Register)

Holds the address of memory to be accessed.

MBR (Memory Buffer Register)

Holds data being read from or written to memory.

I/O AR (I/O Address Register)

Specifies the target I/O device.

I/O BR (I/O Buffer Register)

Temporarily holds data exchanged between CPU and I/O modules.

Instruction Cycle

The process by which a computer fetches and executes instructions stored in memory, consisting of fetch and execute cycles.

Fetch Cycle

The processor reads the next instruction from memory.

Execute Cycle

The processor carries out the instruction, which may involve multiple operations depending on the instruction type.

Program Counter (PC)

Holds the address of the next instruction to be fetched from memory; increments automatically after each fetch unless modified.

Instruction Register (IR)

Stores the fetched instruction, which the processor decodes and executes.

Interrupts

Signals to the processor from I/O and memory modules, temporarily halting normal execution to improve processing efficiency.

Program Interrupt

Generated by conditions occurring during instruction execution, such as arithmetic overflow or division by zero.

Timer Interrupt

Triggered by a processor timer, allowing the operating system to perform periodic tasks.

I/O Interrupt

Generated by an I/O controller to signal operation completion, request processor service, or indicate errors.

Hardware Failure Interrupt

Caused by system failures such as power loss or memory parity errors.

Bus Interconnection

A shared communication pathway connecting major components such as the processor, memory, and I/O. Only one device can transmit at a time to avoid signal conflicts.

Data Bus

Moves data between system components; its width determines how many bits can be transferred at a time.

Address Bus

Specifies the source or destination of data being transferred on the data bus.

Control Bus

Manages access to shared address and data buses, ensuring orderly communication between system components.

Point-to-Point Interconnect

A direct connection between components offering lower latency and higher data rates compared to shared buses.

Intel QuickPath Interconnect (QPI)

A point-to-point interconnect approach introduced in 2008, featuring a memory bus, QPI links, and PCI Express.

QPI Protocol Layer

Defines the data types and format, which consist of multiple Flits.

QPI Routing Layer

Determines the path between nodes in cases where multiple routes exist.

QPI Link Layer

Ensures reliable data transfer and flow control, using 80-bit Flits.

QPI Physical Layer

Handles signal transmission and reception, transferring data in 20-bit units called Phits.

PCI Express (PCIe)

Replaces PCI with a point-to-point interconnect for higher data rates, supporting high-speed I/O devices and prioritizing real-time data streams.

PCIe Endpoint

Standard PCIe devices such as Ethernet, GPU, and Disk Controller.

PCIe Legacy Endpoint

Older devices adapted to PCIe with outdated features.

PCIe Data Link Layer (DLL)

Ensures reliable transmission using flow control and Data Link Layer Packets (DLLPs).

PCIe Transaction Layer (TL)

Generates and processes Transaction Layer Packets (TLPs) and manages data transfer and flow control.