cspp topic 4

memory and storage systems,

what is the main condition to consider when evaluating the properties of storage approaches?

the memory system must facilitate data modification (writing) and data detection (reading)

what factors influence the choice of memory technology?

frequency of access, access time, capacity required, cost (per bit)

what is the designer’s dilemma for memory systems?

the difficulty to balance the desire for low cost and high capacity. and the desire for high performance

what is the memory hierarchy (from top to bottom, where the top is the fastest, most expensive, smallest)?

registers, cache, main store, magnetic disk, tape / optical disk (same level)

why are registers at the top of the memory hierarchy?

they are ultra-fast because they are part of CPU

why is cache at the top half of the memory hierarchy?

very high speed program and data memory

why is main store at the middle of the memory hierarchy?

fast program and data memory

why is magnetic disk at the bottom half of the memory hierarchy?

non-volatile program and data storage, as well as ‘swap’

why are tape and optical disk tied bottom at the memory hierarchy?

both are backup storage, infrequent access, large but very slow

what memory components are random access in the memory hierarchy?

registers, cache, main store

what memory components are sequential access in the memory hierarchy?

magnetic disk, tape, optical disk

why have a memory hierarchy?

economics, temporal locality, spatial locality,

what is temporal locality?

if a particular memory location is referenced, it is likely that the same location will be referenced again in the near future

what is spatial locality?

if a particular memory location is referenced, it is likely that nearby memory locations will be referenced in the near future

complete the sentence: it has been shown that 90% of memory accesses are within ____ of previous position

± 2 kilobytes

what are the main types of semiconductor memory?

RAM, ROM, PROM, EPROM, EEPROM, flash memory

what is RAM?

random access memory, read-write memory, erased electrically at byte level, electrically written, volatile

what is ROM?

read only memory, cannot be erased, mask written, non-volatile

what is PROM?

programmable ROM, read-only, cannot be erased, electrically written, non-volatile

what is EPROM?

erasable PROM, read-mostly, erased with UV-light at chip level, electrically written, non-volatile

what is EEPROM?

electrically erasable PROM, read-mostly, erased electrically at byte level, electrically written, non-volatile

what is flash memory?

read mostly memory, erased electrically at block-level, electrically written, non-volatile

what is cache memory?

based on the assumption that 90% of memory accesses are within only 2 kilobytes, the 2 kilobytes are stored in a small fast cache memory (memory stored close to the CPU)

what is the benefit of cache memory?

if data required by the CU is a ‘cache hit’ (in the cache) big speed improvement

why is cache typically small?

to limit cost

what is Moore’s law?

the number of transistors on a memory chip doubles every 18 months

why is Moore’s law true?

• the cost of computer logic and memory circuitry falls at a dramatic rate

• logic and memory is placed closer together on more densely packed chips so electrical path is shortened, increasing operating speed

• computers have become smaller, making them more convenient for use in a variety of environments, especially embedded systems

• reduction in power and cooling requirements

• interconnections on an IC are more reliable than solder connections, thus having fewer off-chip connections increases reliability

what are the two general strategies that can be adopted when caching writes?

write through, write back

what is the write through strategy for caching writes?

updates the item in cache and writes through to update lower levels of the memory hierarchy

what is the write back strategy for caching writes?

only updates copy in cache, ensures that blocks are copied back to memory when they are able to be replaced

why is caching read-only data relatively straightforward?

we do not need to consider the possibility that items will change, hence copies across the memory hierarchy will remain consistent

what are the main types of cache miss?

compulsory, capacity, conflict, coherency

what is cache miss time?

the delay incurred when the CPU requests data that is not present in the cache and must be fetched from a slower memory level

how is hit rate (h) measured?

h = number of times the words are in cache / total number of memory references

how is cache miss rate calculated?

1-h

what is a compulsory cache miss?

misses that would occur regardless of cache size (eg. the first access to a block can not be in cache so the block must be retrieved)

what is capacity cache miss?

misses occurring because a cache is not large enough to contain all blocks needed during the execution of a program

what is conflict cache miss?

misses occurring as a result of the placement strategy for blocks not being fully associative, which means that a block may be discarded and retrieved

what is coherency cache miss?

misses occurring due to cache flushes in multiprocessor systems

how is average memory access time measured?

average memory access time = hit time + (miss rate * miss penalty)

what is average memory access time?

an alternative measure that accounts for the cost of a cache miss

what is hit time?

the time to hit in the cache

what is miss penalty?

the time taken to replace the block from memory

what is the optimisation concern for memory hierarchy?

we want to use fastest memory possible for high performance, but problems may large datasets

what is the memory hierarchy in relation to cache (from top to bottom)?

L1, L2, L3, main memory, hard disk

how is the memory hierarchy (in relation to cache) organised?

descending order of speed

what are the advantages and disadvantages of hard disk memory?

greatest capacity (out of those in memory hierarchy — cache), does not need continuous power, but has the slowest access times

what are the advantages and disadvantages of main memory?

main memory is further and slower but has a far greater capacity

what is are the advantages and disadvantages of cache?

memory closer to CPU is typically faster but has a far smaller capacity

what is the solution for the optimisation problem (wanting to use fastest memory possible for high performance, but problems may large datasets)?

reuse data already in cache as much as possible and prefetch data from main memory into cache before it is needed masking load times

what are the main two technologies for semiconductor memory?

static RAM (SRAM), dynamic RAM (DRAM)

what is the most common form of main store?

RAM

what does SRAM do?

uses a flip-flop as storage element for each bit

what does DRAM do?

for each bit, use the presence or absence of charge in a capacitor to denote a 1 or 0

what are the advantages and disadvantages of capacitors?

capacitor charge leaks away over time, so requires periodic refreshing (more complex), but is cheaper than SRAM

why is DRAM used more than SRAM?

even with periodic refreshing of capacitors, DRAM is cheaper than SRAM

how does SRAM work?

stores data using configurations of flip-flops and logic gates, memory cells hold data as long as power is supplied

how do SRAM cells achieve a stable logic state?

typical SRAM cells use four cross-couples transistors to establish a stable logic state

how does DRAM work?

DRAM memory cells store data s charge on capacitors, charge naturally discharges, hence DRAM cells require periodic charge to maintain data storage

what does the term ‘dynamic’ refer to in DRAM?

the natural leakage of charge that takes place even when power is applied

what does the transistor do in DRAM?

acts as a switch that is closed (allowing current flow) i fa voltage is applied to the address line and open if a voltage is not applied to the address line (no flow)

describe DRAM write operations.

voltage applied to the bit line, (high for logical 1, low for logical 0), a signal is then applied to the address line, allow a charge to be transferred to the capacitor (data store)

describe DRAM read operation.

• transistor turns on when address line is selected, allowing the stored charge to be fed out to the bit line and a sense amplifier

• sense amplifier compared the capacitor voltage to a predetermined threshold value to determine fi the cell contains a logic 0 or 1

• the read process discharges the capacitor, which means that it must be restores (As well as refreshed) following the read operation

what similarities do SRAM and DRAM have?

both are volatile, power must be continuously applied

what are the advantages of DRAM over SRAM?

dynamic cells are generally simpler and more compact

• allows greater memory cell density (more cells per unit area)

• cheaper to produce than equivalent SRAM memory

what are the advantages of SRAM over DRAM

SRAM typically provide better read and write times than DRAM

• cache memory (on and off chip) is often implemented as SRAM, whilst DRAM is commonly used for main memory

why are advanced DRAM organisations considered?

to achieve better system performance. the interface to man memory is a critical performance bottleneck, there is motivation for multiple high-speed SRAM caches between a processor and DRAM main memory

what advanced DRAM organisations can be considered to achieve better system performance?

synchronous DRAM (SDRAM), rambus DRAM (RDRAM), DDR SDRAM, cache DRAM (CDRAM)

how was an early form of RAM organised?

data is stored through the magnetisation of tiny metal rings, one bit per ring. rings are organised into a grid array, individual bits are accessed by energising row and column wires

how can address decoding space be minimised?

divide the address inputs into 2 parts, row address and column address

what is the benefit of minimising address decoding space?

maximises space used for memory cells

what is noise?

unwanted information

how does noise arise in devices?

thermal noise, noise of electronic components, noise of transmission circuits

why do magnetic media also have a classic form of noise?

random alignment of magnetic fields, decreased area to store a bit means noise gets worse, making errors likely

how is noise immunity achieved and when does it collapse?

digital logic gives us a high degree of noise immunity, immunity collapses once the noise reaches a certain magnitude

what are the disadvantages of majority voting in error checking?

very expensive, if the probability of an error in the channel is low, the probability of two errors is even lower

what is the method of adding a parity bit?

even parity system or odd parity system, where a parity bit is added to the message every so often that summarises a property of the message so we can check whether the message has been altered

how does even parity system work?

the value of the extra it is chosen to make the total number of logic 1s an even number

how does odd parity system work?

make the total number of logic 1s odd

how is parity computed in software?

• if odd, start at even (vice versa)

• may be computed using a two state finite automaton

• each 1 in the message causes a transition of state

• final state at the end of the message is the resulting parity bit

why is computing parity in hardware more popular?

they perform better than software implementations, despite being a relatively simple digitial logic circuit

why is parity ideal?

provides error detection without the need to signifiantly change out model for ocommunication

how does error detection work using parity?

• at the transmitter, a message is encoded

• compute parity and append parity to message

• send modified message across channel

• at our receiver the message, now 8-bits including parity, is decoded

• compute parity from data bits of received message

• compare computed parity with received parity in message and flag error if these are not consistent

what is a burst error?

the idea that in practice, multiple errors often occur in bursts. in contrast, if the probability of an error in the channel is low, the probability of two errors close together is even lower

how can burst errors be detected?

checksum

how does checksum work?

• to send a message over a channel, calculate bit column parity checksum values

• send message with appended checksum

what is an error correcting code?

encodes messages as binary numbers where redundancy is introduced to detect and correct errors, achieved by calculating both character and bit--column parity

how does ECC work?

• at transmitter, we compute character parity bits, then bit-column parity value and transmit

• at receiver, compute character parity bits, ignoring received parity bits

• for each character, compare re-computed character parity with received parity

• if not equal, error somewhere in row

• re-compute bit-column parity value

• compare re-computed value with received value

• if not equal, error somewhere in column

• if a single error detected, correct by inverting bit in message at (row, column)

how do magnetic hard disks work?

• they record data by magnetising a thin film of ferromagnetic material on a disk

• one track contains many sectors

• each sector is separated by an inter-sector gap

• sector contains preamble to allow head to be synchronised before read/write, data and ECC

what are the key points around performance for magnetic hard disks?

• seek times are typically about 5ms between different tracks but can be below 1ms for consecutive tracks

• rotational latency

• sector read time is about 0.013ms, which means that seek time and rotational latency dominate access time

• formatting reduces capacity about 15%

what does rotational latency mean for magnetic hard disks?

constant angular velocity (ie. motor spins at a constant speed), drives available with rotational speeds of 5400RPM, 7200 RPM, or 10800 RPM, average delay = 3 to 6ms

how have hard disks been adapted to increase capacity?

older drives had a constant number of sectors per track, recent disks are zoned (10-30 zones), with more sectors in the longer (outer) tracks. many tracks per zone, more sectors give higher capacity

why do older drives have lower capacity?

they have a constant number of sectors per track, due to constant angular velocity, bit density is lower on outer tracks

why does the zones approach work to give hark disks an increased capacity?

many tracks per zone, more sectors gives higher capacity

what is RAID?

redundant arrays of inexpensive disk, takes multiple hard drives and makes them work rogether as a single,logical storage unit

what are the main aims of RAID?

data redundancy (if one drive fails you don’t lose anything), performance improvement, increased storage capacity

what is RAID 0?

the striping level of RAID, focuses on speed. data is split into stripes and written across multiple drives simultaneously

what are advantages and disadvantages of RAID 0?

very fast, if any drive fails, you lose all your data from the array (no data redundancy)

what is RAID 1?

mirroring, focuses on protection. data is duplicated (mirrored) onto two or more drives, if one drive fails, the other still has a copy of data

what are advantages and disadvantages of RAID 1?

provides excellent redundancy, uses more disk space (since data is copied)