1.1.1 Structure and function of the processor
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Description and Tags
Registers and buses. FDE cycle. Factors affecting the CPUs performance. Pipelining. Computer architecture.
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43 Terms
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Arithmetic Logic Unit (ALU)
\-handles arithmetic and logical operations
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The Control Unit (CU)
\--directs the operations within the CPU
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Jobs of the CU
\-controlling and coordinating the CPUs activities
\-managing the flow of data between the CPU and other devices
\-accepting the next instruction
\-decoding instructions
\-storing the result of operations back in memory
\-managing the flow of data between the CPU and other devices
\-accepting the next instruction
\-decoding instructions
\-storing the result of operations back in memory
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Registers
\-small amounts of high speed memory within the CPU
\-used to temporarily store data
\-used to temporarily store data
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The registers
\-program counter
\-accumulator
\-memory data register
\-current instruction register
\-memory address register
\-accumulator
\-memory data register
\-current instruction register
\-memory address register
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Program counter
\-holds the address of the next instruction to be executed
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Accumulator
\-stores the results of calculations
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memory address register
\-holds the address of a location that is to be read from or written to
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Memory data register
\-temporarily stores the instruction that has been fetch and is waiting to be executed
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Current instruction register
\-holds the current instruction being executed
\-divides the instruction into operand and opcode
\-divides the instruction into operand and opcode
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buses
\-sets of parallel wires that connect components inside the CPU
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bus width
\-width of the bus is the number of parallel wires the bus has
\-width is directly proportional to the number of bits that can be transferred in one go
\-width is directly proportional to the number of bits that can be transferred in one go
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The system bus
\-made up of the data bus, control bus and address bus
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Data bus
\-bi-directional
\-transports instructions and data between components
\-transports instructions and data between components
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Address bus
\-uni-directional
\-transmits the memory address where the data is to be sent to or retrieved from
\-transmits the memory address where the data is to be sent to or retrieved from
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Control bus
\-bi-directional
\-transmits control signals between internal and external components
\-transmits control signals between internal and external components
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Control signals
\-bus request
\-bus grant
\-memory write
\-memory read
\-interrupt request
\-clock
\-bus grant
\-memory write
\-memory read
\-interrupt request
\-clock
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Bus request
\-shows that the device is requesting use of the data bus
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Bus grant
\-shows that the CPU has granted access to the data bus
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memory read
\-data is read from a specific location to be placed on the data bus
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memory write
\-data is written into the addressed location using the control bus
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interrupt request
\-shows that a device is requesting access to the CPU
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clock
\-synchronises the operations of the processor
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Fetch decode execute cycle
\-the sequence of operations that are carried out to execute an instruction
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Fetch
\-address held in the PC is copied to the MAR
\-instruction held at that address is copied to the MDR by the data bus
\-value held in the MDR is copied into the CIR
\-content of the PC is incremented by 1
\-instruction held at that address is copied to the MDR by the data bus
\-value held in the MDR is copied into the CIR
\-content of the PC is incremented by 1
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Decode
\-the content of the CIR are split into operand and opcode
\-the control unit decodes the instruction
\-the control unit decodes the instruction
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Execute
\-the instruction is carried out
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Factor affecting CPU performance
\-clock speed
\-number of cores
\-cache
\-pipelining
\-number of cores
\-cache
\-pipelining
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Clock speed
\-determined by the system clock
\-measured in Hz per second
\-the number of clock cycles completed in one second
\-measured in Hz per second
\-the number of clock cycles completed in one second
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Number of cores
\-each core can carry out its own FDE cycle independently of other cores
\-not all programs are optimised for using multiple cores
\-not all programs are optimised for using multiple cores
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Cache
\-small amount of memory that sits near the CPU
\-fast access
\-stores frequently used instructions and data
\-3 levels
\-fast access
\-stores frequently used instructions and data
\-3 levels
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Level 1 cache
\-very fast
\-small capacity
\-small capacity
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level 2 cache
\-relatively fast
\-medium capacity
\-medium capacity
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Level 3 cache
\-large capacity
\-not very fast
\-not very fast
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pipelining
\-concurrent processing of multiple instruction
\-next instruction is fetched while the current one is decoded and the previous one is executed
\-next instruction is fetched while the current one is decoded and the previous one is executed
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advantages of pipelining
\-reduces the amount of time the CPU is kept idle
\-speeds up execution
\-speeds up execution
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Von Neumann architecture
\-one control unit, ALU, registers and memory
\-data and instructions stored in the same memory and use the same data bus
\-data and instructions stored in the same memory and use the same data bus
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Harvard architecture
\-physically separate memories for instructions and data
\-mainly used with embedded processors
\-mainly used with embedded processors
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Von Neumann advantages
\-cheaper to develop
\-control unit is easier to design
\-programs can be optimised to size
\-control unit is easier to design
\-programs can be optimised to size
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Harvard advantages
\-quicker as data and instructions can be fetched at the same time
\-memories can be different sizes which can make more efficient use of the available space
\-memories can be different sizes which can make more efficient use of the available space
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Contemporary processing
\-combination of Von Neumann and Harvard
\-uses Von Neumann when working with data and instruction in main memory
\-uses Harvard when working with cache
\-instruction cache and data cache
\-uses Von Neumann when working with data and instruction in main memory
\-uses Harvard when working with cache
\-instruction cache and data cache
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RAM
\-random access memory
\-stores data and instruction that are currently being used
\-volatile
\-stores data and instruction that are currently being used
\-volatile
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ROM
\-read only memory
\-stores the BIOS
\-non-volatile
\-stores the BIOS
\-non-volatile