1.1.1 Structure and function of the processor

Registers and buses. FDE cycle. Factors affecting the CPUs performance. Pipelining. Computer architecture.

Arithmetic Logic Unit (ALU)

\-handles arithmetic and logical operations

The Control Unit (CU)

\--directs the operations within the CPU

Jobs of the CU

\-controlling and coordinating the CPUs activities

\-managing the flow of data between the CPU and other devices

\-accepting the next instruction

\-decoding instructions

\-storing the result of operations back in memory

Registers

\-small amounts of high speed memory within the CPU

\-used to temporarily store data

The registers

\-program counter

\-accumulator

\-memory data register

\-current instruction register

\-memory address register

Program counter

\-holds the address of the next instruction to be executed

Accumulator

\-stores the results of calculations

memory address register

\-holds the address of a location that is to be read from or written to

Memory data register

\-temporarily stores the instruction that has been fetch and is waiting to be executed

Current instruction register

\-holds the current instruction being executed

\-divides the instruction into operand and opcode

buses

\-sets of parallel wires that connect components inside the CPU

bus width

\-width of the bus is the number of parallel wires the bus has

\-width is directly proportional to the number of bits that can be transferred in one go

The system bus

\-made up of the data bus, control bus and address bus

Data bus

\-bi-directional

\-transports instructions and data between components

Address bus

\-uni-directional

\-transmits the memory address where the data is to be sent to or retrieved from

Control bus

\-bi-directional

\-transmits control signals between internal and external components

Control signals

\-bus request

\-bus grant

\-memory write

\-memory read

\-interrupt request

\-clock

Bus request

\-shows that the device is requesting use of the data bus

Bus grant

\-shows that the CPU has granted access to the data bus

memory read

\-data is read from a specific location to be placed on the data bus

memory write

\-data is written into the addressed location using the control bus

interrupt request

\-shows that a device is requesting access to the CPU

clock

\-synchronises the operations of the processor

Fetch decode execute cycle

\-the sequence of operations that are carried out to execute an instruction

Fetch

\-address held in the PC is copied to the MAR

\-instruction held at that address is copied to the MDR by the data bus

\-value held in the MDR is copied into the CIR

\-content of the PC is incremented by 1

Decode

\-the content of the CIR are split into operand and opcode

\-the control unit decodes the instruction

Execute

\-the instruction is carried out

Factor affecting CPU performance

\-clock speed

\-number of cores

\-cache

\-pipelining

Clock speed

\-determined by the system clock

\-measured in Hz per second

\-the number of clock cycles completed in one second

Number of cores

\-each core can carry out its own FDE cycle independently of other cores

\-not all programs are optimised for using multiple cores

Cache

\-small amount of memory that sits near the CPU

\-fast access

\-stores frequently used instructions and data

\-3 levels

Level 1 cache

\-very fast

\-small capacity

level 2 cache

\-relatively fast

\-medium capacity

Level 3 cache

\-large capacity

\-not very fast

pipelining

\-concurrent processing of multiple instruction

\-next instruction is fetched while the current one is decoded and the previous one is executed

advantages of pipelining

\-reduces the amount of time the CPU is kept idle

\-speeds up execution

Von Neumann architecture

\-one control unit, ALU, registers and memory

\-data and instructions stored in the same memory and use the same data bus

Harvard architecture

\-physically separate memories for instructions and data

\-mainly used with embedded processors

Von Neumann advantages

\-cheaper to develop

\-control unit is easier to design

\-programs can be optimised to size

Harvard advantages

\-quicker as data and instructions can be fetched at the same time

\-memories can be different sizes which can make more efficient use of the available space

Contemporary processing

\-combination of Von Neumann and Harvard

\-uses Von Neumann when working with data and instruction in main memory

\-uses Harvard when working with cache

\-instruction cache and data cache

RAM

\-random access memory

\-stores data and instruction that are currently being used

\-volatile

ROM

\-read only memory

\-stores the BIOS

\-non-volatile