ECE 20002 — MOSFETs: Classification, DC Bias & Amplifiers (Lectures 1–6)

How many MOSFET device types does Lukens draw, and what are they?

Four: NMOS enhancement, NMOS depletion, PMOS enhancement, PMOS depletion.

On a MOSFET symbol, which terminal is the source?

The terminal with the arrow. (G = gate, D = drain, S = source.)

How do you tell enhancement from depletion on the symbol?

Enhancement is drawn with a broken channel; depletion is drawn with a solid (shaded) channel bar.

How are NMOS vs PMOS drawn in Lukens's notes?

NMOS: D on top, S on bottom. PMOS: S on top, D on bottom.

enhancement ⟺ ? depletion ⟺ ?

enhancement ⟺ normally OFF; depletion ⟺ normally ON. "Normal" means V_GS = 0.

NMOS enhancement: sign of V_Th?

V_Th > 0 (normally off).

NMOS depletion: sign of V_Th?

V_Th < 0 (normally on).

PMOS enhancement: sign of V_Th?

V_Th < 0 (normally off).

PMOS depletion: sign of V_Th?

V_Th > 0 (normally on).

Give the full device / V_Th pairing table (memorize — Lukens tests this).

NMOS enh: V_Th > 0 • NMOS dep: V_Th < 0 • PMOS enh: V_Th < 0 • PMOS dep: V_Th > 0

Which device types share V_Th > 0?

NMOS enhancement and PMOS depletion.

Which device types share V_Th < 0?

NMOS depletion and PMOS enhancement.

Sign convention for λ by device?

λ > 0 for NMOS; λ < 0 for PMOS.

What is k (or k_n), and what are its units?

The transconductance parameter, units mA/V². It is a PROPERTY OF THE MOSFET, not of the circuit.

What single piece of information determines the regime of operation?

The ordered pair (V_GS, V_DS).

What are the three regions of operation?

Cutoff, triode, saturation.

I_D in cutoff?

I_D = 0

I_D in triode?

I_D = k [ (V_GS − V_Th)·V_DS − V_DS²/2 ]

I_D in saturation?

I_D = (k/2)(V_GS − V_Th)²

Equation of the triode/saturation boundary?

V_DS = V_GS − V_Th

NMOS enhancement: condition for cutoff?

V_GS < V_Th

NMOS enhancement: condition for saturation?

V_GS > V_Th AND V_DS > V_GS − V_Th

NMOS enhancement: condition for triode?

V_GS > V_Th AND 0 < V_DS < V_GS − V_Th

On the NMOS regime plot (V_GS horizontal, V_DS vertical), where is each region?

Left of the dashed V_Th line = cutoff. Right of V_Th: above the line V_DS = V_GS − V_Th → saturation; below it → triode. V_DS < 0 is hatched out ("don't touch V_DS < 0").

On the PMOS regime plot, where is each region?

V_DS > 0 is hatched out. Right of the dashed V_Th line = cutoff. Left of it: above the line V_DS = V_GS − V_Th (toward V_DS = 0) → triode; below it → saturation.

How does the NMOS depletion regime plot differ from NMOS enhancement?

Identical picture, but V_Th < 0 puts the dashed V_Th line to the LEFT of the origin.

How does the PMOS depletion regime plot differ from PMOS enhancement?

Identical picture, but V_Th > 0 puts the dashed V_Th line to the RIGHT of the origin.

V_GS fixed, V_DS swept: sketch I_D vs V_DS for NMOS enhancement.

If V_GS < V_Th: I_D = 0, flat. If V_GS > V_Th: I_D rises along the triode curve then flattens into saturation; the knee is at V_DS = V_GS − V_Th.

V_DS fixed, V_GS swept: sketch I_D vs V_GS for NMOS enhancement (V_DS > 0).

I_D = 0 up to V_GS = V_Th (cutoff) → quadratic rise from V_Th to V_DS + V_Th (saturation) → nearly linear beyond V_GS = V_DS + V_Th (triode).

What is the typical goal of a DC MOSFET bias circuit?

Produce a desired I_D with the device in saturation.

Name the elements of the standard four-resistor bias network.

R_1 and R_2 form the gate divider (current I_1) between V+ and V−; R_D from V+ to the drain; R_SS from the source to V−. Note the double S in R_SS.

What is I_G at DC, and why does it matter?

I_G = 0, so the gate divider carries a single current I_1 and V_G is set purely by R_1, R_2.

Formula for the gate-divider current I_1?

I_1 = (V+ − V−) / (R_1 + R_2)

Formula for V_G in the four-resistor bias network?

V_G = V+ − R_1·I_1 = V+ − [R_1/(R_1 + R_2)]·(V+ − V−)

Formulas for V_D and V_S (always true, any regime)?

V_D = V+ − R_D·I_D and V_S = V− + R_SS·I_D — both come from full KVL.

State Lukens's 4-step procedure for solving a DC MOSFET bias circuit.

① Find V_G if possible. ② Write V_GS & V_DS in terms of I_D. ③ Assume saturation & solve for I_D. ④ Check (V_GS, V_DS) for consistency with saturation — if yes, done; if no, assume triode and repeat ③–④.

Solving in saturation gives a quadratic in I_D — what are the two possible outcomes?

Either exactly one root works for saturation, or neither does (then re-solve assuming triode).

How do you reject a spurious I_D root?

Back-substitute: compute V_GS and V_DS for that root and test them. V_GS < V_Th ⇒ cutoff. V_DS < V_GS − V_Th ⇒ triode, not saturation.

Example 1 (R_1 = 3 MΩ, R_2 = 2 MΩ, V+ = 5 V, V− = −5 V): what is V_G?

V_G = 5 − (3/5)(10) = −1 V

Example 1: with R_SS = 2 kΩ and V_G = −1 V, write V_GS in terms of I_D.

V_GS = V_G − V_S = −1 − (−5 + 2k·I_D) = 4 − 2k·I_D

Example 1: with R_D = 1 kΩ and R_SS = 2 kΩ, write V_DS in terms of I_D.

V_DS = (5 − 1k·I_D) − (−5 + 2k·I_D) = 10 − 3k·I_D

Example 1: roots are I_D = 1 mA and 9/4 mA. Which is valid, and why?

I_D = 1 mA. It gives V_GS = 2 V > V_Th = 1 V and V_DS = 7 V > V_GS − V_Th = 1 V ⇒ saturation. The 9/4 mA root gives V_GS = −½ V < V_Th ⇒ cutoff.

Example 2 changes only R_D to 8 kΩ. Why does the saturation assumption fail?

V_DS = 10 − 10k·I_D = 0 at I_D = 1 mA, which is not > V_GS − V_Th. The device is in triode, so re-solve with the triode equation ⇒ I_D = 0.9431 mA.

If k is not given but an operating point is, how do you find it?

Use any stated operating point (Ĩ_D, Ṽ_GS): k = 2·Ĩ_D / (Ṽ_GS − V_Th)²

State Lukens's 5-step procedure for DESIGNING a DC operating point.

① Begin with a target I_D. ② Assume saturation & find V_GS. ③ Target |V_DS| ≈ ½(V+ − V−). ④ Choose R_D & R_SS to achieve V_DS. ⑤ Choose R_1 & R_2 to achieve V_GS.

Inverting the saturation equation for V_GS?

V_GS = V_Th ± √( 2·I_D / k ) — pick the sign that keeps the device out of cutoff.

Design example: V_Th = −2 V, k_n = 2 mA/V², target I_D = 1 mA. Find V_GS.

V_GS = −2 ± √(2·1m / 2m) = −2 ± 1 = −1 V (choose −1 V so it is not in cutoff).

Why target |V_DS| ≈ ½(V+ − V−)?

It centers the operating point in the rail-to-rail range, leaving maximum headroom while maintaining saturation.

Which KVL sets R_D + R_SS in a design problem?

−V+ + R_D·I_D + V_DS + R_SS·I_D + V− = 0 ⇒ R_D + R_SS = (V+ − V− − V_DS)/I_D

Which KVL sets V_G once R_SS is picked?

−V_G + V_GS + R_SS·I_D − V+ = 0 (loop through gate, source, bottom rail). Then choose R_1, R_2 to give that V_G.

What is a current mirror?

Two identical MOSFETs sharing a gate node, where M_1 has its drain tied to its gate (diode-connected). With both in saturation, I_2 = I_1.

Prove I_2 = I_1 for a current mirror.

Both devices share V_G and have grounded sources, so V_GS1 = V_GS2 = V_G. Then I_1 = (k_n/2)(V_G − V_Th)² = I_2.

Why can M_1 in a current mirror never be in triode?

D_1 is tied to G_1, so V_DS1 = V_GS1 and the saturation test V_DS1 > V_GS1 − V_Th collapses to 0 > −V_Th, which is automatically satisfied.

What can push M_2 of a current mirror out of saturation?

The surrounding circuit. With V+ in series with R_2 into D_2, saturation needs V+ − R_2·I_1 > V_G − V_Th. If R_2·I_1 gets too big, M_2 goes triode even though M_1 is still saturated.

What happens with three or more mirrored MOSFETs?

I_2 = I_1, I_3 = I_1, … — a current multiplier. Works as long as the surrounding circuit keeps every transistor in saturation.

State the case convention for DC, AC, and total quantities.

UPPER symbol/UPPER subscript = DC (I_D, V_GS). lower/lower = AC small signal (i_d, v_gs). lower symbol/UPPER subscript = total (i_D, v_GS). So i_D = I_D + i_d, v_GS = V_GS + v_gs, v_DS = V_DS + v_ds.

State the small-signal assumption.

|i_d| ≪ |I_D| , |v_gs| ≪ |V_GS| , |v_ds| ≪ |V_DS|

What mathematical procedure produces the small-signal model?

A first-order Taylor expansion of i_D about the DC point (V_GS, V_DS).

Write the general small-signal drain-current expansion.

i_d = (∂i_D/∂v_GS)|_DC · v_gs + (∂i_D/∂v_DS)|_DC · v_ds

Formula for g_m?

g_m = √( 2·k·I_D ) — from (∂i_D/∂v_GS)|_DC = ± k|V_GS − V_Th| = ± √(2k·I_D).

Formula for r_o?

r_o = 1 / ( |λ|·I_D ) — from (∂i_D/∂v_DS)|_DC = I_D·λ = ± 1/r_o.

Saturation formula WITH channel-length modulation?

i_D = (k/2)(v_GS − V_Th)² · { 1 + λ[ v_DS − (v_GS − V_Th) ] }

Biggest warning about the channel-length-modulation formula?

NEVER use it for DC analysis. It is saturation-only, and exists to derive the small-signal model.

What does λ = 0 imply?

λ = 0 ⟺ r_o = ∞ ⟺ neglect channel-length modulation.

Describe the small-signal MOSFET model.

Gate g with + v_gs − down to source s; between d and s a dependent current source g_m·v_gs in parallel with r_o. Match g, d, s to the circuit's G, D, S nodes.

How do the NMOS and PMOS small-signal models compare?

IDENTICAL, as long as the g, d, s nodes are respected — the direction of i_d is only a convention.

What does channel-length modulation do to the i_D vs v_DS curve?

λ = 0 ⇒ the saturation region is flat. λ ≠ 0 ⇒ the saturation region slopes upward.

What is inside the two-port voltage-amplifier model?

Only resistors and dependent sources: input port v_i across R_i; output port a dependent source A_o·v_i in series with R_o. Valid for unilateral amplifiers (no backaction from v_o to v_i).

Describe the INPUT test.

Drive v_x with current i_x into the input port and observe v_o at the open output: R_i = v_x/i_x , A_o = v_o/v_x

Describe the OUTPUT test.

Kill the input source, then drive v_x with current i_x into the output port: R_o = v_x/i_x

Loaded gain formula with source resistance R_s and load R_L?

A = A_o · [R_i/(R_s + R_i)] · [R_L/(R_o + R_L)] ≤ A_o

What R_i and R_o do we want, and why?

High input impedance, low output impedance. R_i = ∞ and R_o = 0 give A = A_o regardless of R_s and R_L.

Sign rule for gains vs resistances?

A minus sign is fine for a gain (A_o = −g_m(r_o‖R_D)) but NEVER for a resistance (R_i or R_o).

Define the common-source (CS) amplifier.

The source is grounded / common to both the input (V_GS) and the output (V_DS).

Why are C_1, C_2, C_3 used, and what are they assumed to be?

Series (coupling) capacitors let AC signals in and out without disturbing the DC bias. Since Z_C = 1/(jωC), assume C_1, C_2, C_3 ≈ ∞ at the frequencies of interest.

State the 3 steps to obtain the AC small-signal (mid-frequency) circuit.

① Short (open) all DC voltage (current) sources. ② Convert the MOSFET to its small-signal version. ③ Short (open) external (internal) capacitors.

Give the CS / CD / CG configuration table.

CS: v_g = v_i, v_s = 0, v_d = v_o • CD: v_g = v_i, v_s = v_o, v_d = 0 • CG: v_g = 0, v_s = v_i, v_d = v_o

What is R_1 ‖ R_2 shorthand for?

The parallel combination (R_1·R_2)/(R_1 + R_2).

CS amplifier: R_i, A_o, R_o?

R_i = R_1‖R_2 • A_o = −g_m(r_o‖R_D) • R_o = r_o‖R_D

CD amplifier: R_i, A_o, R_o?

R_i = R_1‖R_2 • A_o = g_m(r_o‖R_SS) / [1 + g_m(r_o‖R_SS)] • R_o = (r_o‖R_SS)/[1 + g_m(r_o‖R_SS)] = (1/g_m)‖(r_o‖R_SS)

CG amplifier (with r_o = ∞): R_i, A_o, R_o?

R_i = R_SS/(1 + g_m·R_SS) = (1/g_m)‖R_SS • A_o = g_m·R_D • R_o = R_D

Which configuration inverts the signal?

Only CS — its A_o = −g_m(r_o‖R_D) carries the minus sign. CD and CG have positive A_o.

Which configuration is the buffer, and why?

CD (source follower): A_o = g_m(r_o‖R_SS)/[1 + g_m(r_o‖R_SS)] is just under 1, with high R_i = R_1‖R_2 and low R_o = (1/g_m)‖(r_o‖R_SS).

Which configuration has low input resistance?

CG: R_i = (1/g_m)‖R_SS, because the input drives the source node directly.

General advice for running the input/output tests on a small-signal circuit?

① Start with KCL at the v_x and/or v_o nodes. ② Use KVL to write v_gs in terms of v_x, v_o, i_x.

CS input test: what do the KCL and KVL equations reduce to?

KCL: i_x = v_gs/(R_1‖R_2) and g_m·v_gs + v_o/(r_o‖R_D) = 0. KVL: v_gs = v_x. Hence R_i = R_1‖R_2 and A_o = −g_m(r_o‖R_D).

CS output test: why does R_o come out so simply?

With the input killed, KVL gives v_gs = 0, so the dependent source is dead and R_o = r_o‖R_D.

CD input test: what is the KVL relation, and why does it change A_o?

−v_x + v_gs + v_o = 0 ⇒ v_gs = v_x − v_o. The output feeds back into v_gs, producing the 1 + g_m(r_o‖R_SS) denominator.

CG input test: what is the v_gs polarity relation?

The gate is AC-grounded and the input drives the source, so v_gs = −v_x. This gives R_i = (1/g_m)‖R_SS and A_o = +g_m·R_D.

Why is the CG amplifier usually analyzed with r_o = ∞?

Lukens derives the CG results assuming λ = 0 (r_o = ∞) to keep the algebra tractable; R_D then sets both A_o and R_o.

What does the textbook add to the CS/CD/CG formulas that Lukens omits?

The load resistance R_L. It can be added to these formulas as desired.