Analog

What does an ideal op amp assume

infinite input impedance plus infinite open loop gain plus virtual short V+ approximately V- plus zero noise and infinite bandwidth

What is the inverting amplifier formula

Vout = -Vin Rf/Rin

What is the current summer formula

Vout = -Rf(V1/R1 + V2/R2 + … + Vn/Rn)

What does an analog buffer do

it preserves voltage while isolating the input circuit from the output circuit

Why is a buffer useful in sample and hold

it lets the capacitor charge quickly when sampling and prevents the ADC from draining charge while holding

What does a comparator output

it outputs high or low depending on whether the input voltage is above or below Vref

What happens when a bus master writes to an analog output port

the digital register value is converted by a DAC into an analog voltage

What happens when a bus master requests analog input

the interface samples the analog voltage starts ADC conversion then sets Data Valid when done

What are the two core analog interfacing issues

quantization in the value domain and sampling in the time domain

What is an LSB

the smallest analog voltage change represented by one digital code step

For an n bit unipolar converter what is Vmax

Vmax = (2^n - 1)LSB

For an n bit unipolar converter what is LSB from full scale range

LSB = Vfullscale/(2^n - 1)

For a 0 V to 10 V 10 bit converter what is 1 LSB

10/1023 = 9.76 mV

For 2s complement bipolar conversion what are the min and max analog values

Vmin = -2^(n-1)LSB and Vmax = (2^(n-1)-1)LSB

For sign magnitude bipolar conversion what are the min and max analog values

Vmin = -(2^(n-1)-1)LSB and Vmax = (2^(n-1)-1)LSB

What is biased low ADC quantization error

the output is rounded down and error is in (-LSB to 0]

What is biased high ADC quantization error

the output is rounded up and error is in [0 to LSB)

What is unbiased ADC quantization error

the error range is [-0.5LSB to +0.5LSB]

What is the Nyquist sampling rule

sample at least 2f for a signal with significant frequency content below f

What is the sample period limit from Nyquist

Ts < 1/(2f)

What is aperture time

the time interval where the sampled output is sensitive to input changes

What aperture time rule is used in this course

limit input change during aperture to at most 1/4 LSB

If maximum signal slope is S what aperture time is acceptable

Taperture <= (0.25LSB)/S

For a sine wave with peak voltage Vp and frequency f what is maximum slope

Smax = 2pif*Vp

For LSB = 1 mV and sine Vp = 10 V and f = 200 Hz what aperture time is about

0.25 mV/(2pi200*10) = about 20 ns

For max slope 4 V/s with a 10 bit 0 to 10 V ADC what aperture time is acceptable

LSB = 9.76 mV so 0.25LSB = 2.44 mV and Taperture <= 610 us

In sample and hold what happens when the sample switch is on

the capacitor voltage tracks Vin

In sample and hold what happens when the sample switch is off

the capacitor holds the last sampled voltage

Why does an ADC input port need consumer responsive generation

the consumer must request a sample and wait for Data Valid

Why does a DAC output port use spontaneous generation

the written digital value can continuously drive the analog output without a request handshake

What is the binary weighted DAC output formula

Vout = -Rf Vref sum(Bi/Ri)

For a binary weighted DAC why do resistor values become a problem

large n requires a huge spread of resistor values that is hard to fabricate accurately

In a binary weighted DAC with R0 as LSB resistor how do higher bit resistors scale

R1 = R0/2 and R2 = R0/4 and R3 = R0/8

In assignment 9 if R0 = 200 ohm what are R1 R2 R3

R1 = 100 ohm and R2 = 50 ohm and R3 = 25 ohm

How do you check op amp current limit in a DAC

set all bits to 1 and sum the branch currents through the summer

In assignment 9 with Vref = 5 V and resistors 200 100 50 25 ohm what is max current

5/200 + 5/100 + 5/50 + 5/25 = 375 mA

Why was that assignment 9 binary weighted DAC not suitable

the op amp limit was 35 mA and required sink current was 375 mA

What does a double throw switch fix in a DAC

it keeps input impedance constant for Vref

What cost comes with double throw DAC switching

it always consumes maximum power

What is the key advantage of an R-2R ladder DAC

it only needs resistor values R and 2R

What matters for an R-2R ladder DAC

the resistance ratio matters rather than the absolute value of R

If all R-2R ladder resistors increase by exactly 10 percent what happens to Vout

Vout stays the same because ratios stay the same

If all R-2R ladder resistors increase by exactly 10 percent what happens to current

current decreases by a factor of 1/1.1

If only the R resistors in an R-2R ladder increase by 10 percent what happens

the current split is no longer ideal and the DAC becomes nonlinear

For an ideal R-2R DAC with Rf = R what is Vout

Vout = -Vref(BMSB/2 + next/4 + … + B0/2^n)

For an ideal R-2R DAC what is LSB

LSB = -Vref/2^n when Vref is negative for positive output

For a 3 bit R-2R DAC with ideal full scale 3.5 V what is LSB

LSB = 3.5/7 = 0.5 V

For a 3 bit R-2R DAC with LSB 0.5 V what is Vref

Vref = -2^3*0.5 = -4 V

For a DAC defined by Vout = k Vref B what is full scale output

VFS = k Vref(2^n - 1)

For a 3 bit DAC with k = 1/8 and desired VFS = 1.4 V what Vref is needed

Vref = 1.4/((1/8)*7) = 1.6 V

For that same 3 bit DAC what is LSB

LSB = k Vref = 0.2 V

What is offset error for a DAC

abs(Vactual(0) - Videal(0))

What is gain error for a DAC after offset is removed

abs(actual full scale after offset - ideal full scale)/ideal full scale

How do you calibrate DAC offset and gain

first subtract offset then divide by 1 plus or minus gain error

What is INL for a DAC after calibration

maximum abs(Vactual(i) - Videal(i))

What is DNL for a DAC

maximum abs(actual step size - 1LSB)

How do you find actual step size for DNL

Vactual(i+1) - Vactual(i)

When can a DAC be nonmonotone

when some higher digital input gives lower analog output than the previous code

What DNL condition warns monotonicity may fail

DNL greater than 1 LSB

In final style table ideal 0 1 2 3 and actual 0.2 1.52 2.18 3.5 what is LSB

1 V

For that same table what is offset error

0.2 V

For that same table what is DNL without calibration

steps are 1.32 0.66 1.32 so max deviation from 1 is 0.34 V

For that same table what is INL without calibration

max abs actual minus ideal is 0.52 V

For that same table what is gain error

after offset full scale is 3.3 V vs ideal 3 V so gain error is 10 percent

In final 2019 actual table 0.2 0.62 1.74 2.3 with ideal 0 0.5 1 1.5 what is calibration

subtract 0.2 then divide by 1.4

In that final 2019 table what are calibrated outputs

0 V 0.3 V 1.1 V 1.5 V

In that final 2019 calibrated table what are DNL and INL

DNL = 0.3 V and INL = 0.2 V

In final 2022 actual table -0.2 0.88 1.51 2.5 with ideal 0 1 2 3 what is calibration

add 0.2 then divide by 0.9

In that final 2022 table what are calibrated outputs

0 V 1.2 V 1.9 V 3 V

In final f2024 ideal 0 0.5 1 1.5 2 2.5 3 3.5 and actual 0 0.45 1.15 1.75 2.35 2.8 2.75 3.5 is the DAC monotone

no because 2.75 is less than 2.8

In that final f2024 table what is DNL percent of LSB

the largest bad step is -0.05 V so abs(-0.05 - 0.5) = 0.55 V = 110 percent of LSB

In that final f2024 table what is INL percent of LSB

max deviation is 0.35 V and LSB is 0.5 V so INL = 70 percent

In an ideal 3 bit R-2R DAC with Vref = -4 V and max current 15 mA what is minimum R

max current = 7/8*4/R = 3.5/R so R >= 233 ohm

For a binary weighted DAC final question how do you compute each bit contribution

use contribution = -Rf Vref/Rbit when that bit is 1

In final 2018 with Vref = -8 V and Vout/(0.5R) = -Vref(B2/0.8R + B1/2R + B0/5R) what are bit weights

B2 = 5 V and B1 = 2 V and B0 = 0.8 V

In final 2022 with Vout/(0.4R) = -Vref(B2/R + B1/1.6R + B0/4R) and Vref = -8 V what are bit weights

B2 = 3.2 V and B1 = 2 V and B0 = 0.8 V

In final 2019 R-2R with Vref = -6 V what were actual bit weights

B2 = 3 V and B1 = 2 V and B0 = 0.5 V

What is a binary ramp ADC

it counts upward and uses an internal DAC until DAC output exceeds Vin

What bias does a binary ramp ADC have

biased high

What is binary ramp ADC minimum and maximum conversion time

min 1 cycle and max 2^n cycles

What is the binary ramp output for 3 bit Vref = -8 V and Vin = 2.7 V

LSB = 1 V and output is 011 because 3 V is first level above 2.7 V

Why can binary ramp ADCs have glitches

multiple counter bits can change at once and the DAC may briefly overshoot

What clock limit applies to a binary ramp ADC internal DAC

the clock period must be at least the DAC settling time for 1 LSB

If DAC settling time is 5 ns what is max ADC clock frequency

1/5 ns = 200 MHz

What is a SAR ADC

it performs binary search by trying bits from MSB to LSB

What bias does a SAR ADC have

biased low

What is SAR ADC conversion time

n cycles for n bits

What rule decides each SAR bit

if DAC output is less than Vin keep the bit and if DAC output is greater than Vin reset the bit

For a 4 bit SAR with 2 V at 0000 and 17 V at 1111 what is LSB

1 V

For that SAR with Vin = 8.1 V what trial sequence gives the answer

1000 gives 10 V reset then 0100 gives 6 V keep then 0110 gives 8 V keep then 0111 gives 9 V reset

For that SAR with Vin = 8.1 V what is final output

0110

For bipolar SAR with V = (B-8)LSB and actual DAC offset +0.5 V what actual DAC formula is used

Vactual = (B-8)LSB + 0.5 V

For that bipolar SAR with LSB = 1 V and Vin = -1.9 V what are trial DAC outputs

B=8 gives 0.5 V reset then B=4 gives -3.5 V keep then B=6 gives -1.5 V reset then B=5 gives -2.5 V keep

For that bipolar SAR with Vin = -1.9 V what is final output

B = 5 or 0101

What is a flash ADC

it compares Vin against all thresholds in parallel using 2^n - 1 comparators

What is flash ADC conversion time

1 cycle independent of n

Why are flash ADCs expensive

they need 2^n - 1 comparators

What bias does the flash ADC use in these lectures

biased low

For an ideal 2 bit flash ADC with Vref = 4 V what are thresholds

1 V and 2 V and 3 V

For that ideal 2 bit flash ADC what are output ranges

[0 1) -> 00 and [1 2) -> 01 and [2 3) -> 10 and [3 4) -> 11